[U-Boot] [PATCH 51/51] mpc83xx: Add gazerbeam board
Simon Glass
sjg at chromium.org
Wed Jul 19 09:07:11 UTC 2017
Hi Mario,
On 14 July 2017 at 05:55, Mario Six <mario.six at gdsys.cc> wrote:
> From: Dirk Eibach <dirk.eibach at gdsys.cc>
>
> The gdsys gazerbeam board is based on a Freescale MPC8308 SOC.
> It boots from NOR-Flash, kernel and rootfs are stored on
> SD-Card.
>
> On board peripherals include:
> - 2x 10/100 Mbit/s Ethernet (optional)
>
> Signed-off-by: Dirk Eibach <dirk.eibach at gdsys.cc>
> Signed-off-by: Mario Six <mario.six at gdsys.cc>
> ---
>
> arch/powerpc/cpu/mpc83xx/Kconfig | 3 +
> arch/powerpc/dts/.gitignore | 1 +
> arch/powerpc/dts/Makefile | 15 +
> board/gdsys/common/Makefile | 1 +
> board/gdsys/common/ioep-fpga.c | 617 ++++++++++++++++++++++++++++++---------
> board/gdsys/mpc8308/Kconfig | 19 ++
> board/gdsys/mpc8308/MAINTAINERS | 2 +
> board/gdsys/mpc8308/Makefile | 1 +
> board/gdsys/mpc8308/gazerbeam.c | 332 +++++++++++++++++++++
> configs/gazerbeam_defconfig | 76 +++++
> include/configs/gazerbeam.h | 484 ++++++++++++++++++++++++++++++
> include/fdt_fixup.h | 5 +
> 12 files changed, 1416 insertions(+), 140 deletions(-)
> create mode 100644 arch/powerpc/dts/.gitignore
> create mode 100644 arch/powerpc/dts/Makefile
> create mode 100644 board/gdsys/mpc8308/gazerbeam.c
> create mode 100644 configs/gazerbeam_defconfig
> create mode 100644 include/configs/gazerbeam.h
>
> diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
> index cdd21a253a..0790b47aa4 100644
> --- a/arch/powerpc/cpu/mpc83xx/Kconfig
> +++ b/arch/powerpc/cpu/mpc83xx/Kconfig
> @@ -91,6 +91,9 @@ config TARGET_STRIDER
> bool "Support strider"
> select SYS_FSL_ERRATUM_ESDHC111
>
> +config TARGET_GAZERBEAM
> + bool "Support gazerbeam"
Need description of the board, URL, etc.
> +
> endchoice
>
> source "board/esd/vme8349/Kconfig"
> diff --git a/arch/powerpc/dts/.gitignore b/arch/powerpc/dts/.gitignore
> new file mode 100644
> index 0000000000..b60ed208c7
> --- /dev/null
> +++ b/arch/powerpc/dts/.gitignore
> @@ -0,0 +1 @@
> +*.dtb
> diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
> new file mode 100644
> index 0000000000..7a0c61ffaa
> --- /dev/null
> +++ b/arch/powerpc/dts/Makefile
> @@ -0,0 +1,15 @@
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb
> +
> +targets += $(dtb-y)
> +
> +DTC_FLAGS += -R 4 -p 0x1000
> +
> +PHONY += dtbs
> +dtbs: $(addprefix $(obj)/, $(dtb-y))
> + @:
> +
> +clean-files := *.dtb
These two files should be added along with your DT I think, not in
this patch. Your board patch should just add the dtb-$(CONFIG... line
above.
> diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile
> index 6f2fea207f..52561db2e1 100644
> --- a/board/gdsys/common/Makefile
> +++ b/board/gdsys/common/Makefile
> @@ -13,3 +13,4 @@ obj-$(CONFIG_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o
> obj-$(CONFIG_STRIDER) += fanctrl.o
> obj-$(CONFIG_STRIDER_CON) += osd.o
> obj-$(CONFIG_STRIDER_CON_DP) += osd.o
> +obj-$(CONFIG_TARGET_GAZERBEAM) += osd.o ihs_mdio.o ioep-fpga.o
> diff --git a/board/gdsys/common/ioep-fpga.c b/board/gdsys/common/ioep-fpga.c
> index a666b93445..24585672f6 100644
> --- a/board/gdsys/common/ioep-fpga.c
> +++ b/board/gdsys/common/ioep-fpga.c
> @@ -11,231 +11,568 @@
>
> #include <gdsys_fpga.h>
>
> -enum {
> - UNITTYPE_MAIN_SERVER = 0,
> - UNITTYPE_MAIN_USER = 1,
> - UNITTYPE_VIDEO_SERVER = 2,
> - UNITTYPE_VIDEO_USER = 3,
> +enum pcb_video_type {
> + PCB_DVI_SL,
> + PCB_DP_165MPIX,
> + PCB_DP_300MPIX,
> + PCB_HDMI,
> + PCB_DP_1_2,
> + PCB_HDMI_2_0,
> };
>
> -enum {
> - UNITTYPEPCB_DVI = 0,
> - UNITTYPEPCB_DP_165 = 1,
> - UNITTYPEPCB_DP_300 = 2,
> - UNITTYPEPCB_HDMI = 3,
> +enum pcb_transmission_type {
> + PCB_CAT_1G,
> + PCB_FIBER_3G,
> + PCB_CAT_10G,
> + PCB_FIBER_10G,
> };
>
> -enum {
> - COMPRESSION_NONE = 0,
> - COMPRESSION_TYPE_1 = 1,
> - COMPRESSION_TYPE_1_2 = 3,
> - COMPRESSION_TYPE_1_2_3 = 7,
> +enum carrier_speed {
> + CARRIER_SPEED_1G,
> + CARRIER_SPEED_3G,
> + CARRIER_SPEED_2_5G = CARRIER_SPEED_3G,
> + CARRIER_SPEED_10G,
> };
>
> -enum {
> - AUDIO_NONE = 0,
> - AUDIO_TX = 1,
> - AUDIO_RX = 2,
> - AUDIO_RXTX = 3,
> +enum ram_config {
> + RAM_DDR2_32BIT_295MBPS,
> + RAM_DDR3_32BIT_590MBPS,
> + RAM_DDR3_48BIT_590MBPS,
> + RAM_DDR3_64BIT_1800MBPS,
> + RAM_DDR3_48BIT_1800MBPS,
> };
>
> -enum {
> - SYSCLK_147456 = 0,
> +enum sysclock {
> + SYSCLK_147456,
> };
>
> -enum {
> - RAM_DDR2_32 = 0,
> - RAM_DDR3_32 = 1,
> - RAM_DDR3_48 = 2,
> +struct fpga_versions {
> + bool video_channel;
> + bool con_side;
> + enum pcb_video_type pcb_video_type;
> + enum pcb_transmission_type pcb_transmission_type;
> + unsigned int hw_version;
> };
>
> -enum {
> - CARRIER_SPEED_1G = 0,
> - CARRIER_SPEED_2_5G = 1,
> +struct fpga_features {
> + u8 video_channels;
> + u8 carriers;
> + enum carrier_speed carrier_speed;
> + enum ram_config ram_config;
> + enum sysclock sysclock;
> +
> + bool pcm_tx;
> + bool pcm_rx;
> + bool spdif_tx;
> + bool spdif_rx;
> + bool usb2;
> + bool rs232;
> + bool compression_type1;
> + bool compression_type2;
> + bool compression_type3;
> + bool interlace;
> + bool osd;
> + bool compression_pipes;
> };
>
> -bool ioep_fpga_has_osd(unsigned int fpga)
> +#ifdef CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM
> +
> +static int get_versions(unsigned int fpga, struct fpga_versions *versions)
> {
> - u16 fpga_features;
> - unsigned feature_osd;
> + enum {
> + VERSIONS_FPGA_VIDEO_CHANNEL = BIT(12),
> + VERSIONS_FPGA_CON_SIDE = BIT(13),
> + VERSIONS_FPGA_SC = BIT(14),
> + VERSIONS_PCB_CON = BIT(9),
> + VERSIONS_PCB_SC = BIT(8),
> + VERSIONS_PCB_VIDEO_MASK = 0x3 << 6,
> + VERSIONS_PCB_VIDEO_DP_1_2 = 0x0 << 6,
> + VERSIONS_PCB_VIDEO_HDMI_2_0 = 0x1 << 6,
> + VERSIONS_PCB_TRANSMISSION_MASK = 0x3 << 4,
> + VERSIONS_PCB_TRANSMISSION_FIBER_10G = 0x0 << 4,
> + VERSIONS_PCB_TRANSMISSION_CAT_10G = 0x1 << 4,
> + VERSIONS_PCB_TRANSMISSION_FIBER_3G = 0x2 << 4,
> + VERSIONS_PCB_TRANSMISSION_CAT_1G = 0x3 << 4,
> + VERSIONS_HW_VER_MASK = 0xf << 0,
> + };
> + u16 raw_versions;
> +
> + memset(versions, 0, sizeof(struct fpga_versions));
> +
> + FPGA_GET_REG(fpga, versions, &raw_versions);
> +
> + versions->video_channel = raw_versions & VERSIONS_FPGA_VIDEO_CHANNEL;
> + versions->con_side = raw_versions & VERSIONS_FPGA_CON_SIDE;
> +
> + switch (raw_versions & VERSIONS_PCB_VIDEO_MASK) {
> + case VERSIONS_PCB_VIDEO_DP_1_2:
> + versions->pcb_video_type = PCB_DP_1_2;
> + break;
> +
> + case VERSIONS_PCB_VIDEO_HDMI_2_0:
> + versions->pcb_video_type = PCB_HDMI_2_0;
> + break;
> + }
> +
> + switch (raw_versions & VERSIONS_PCB_TRANSMISSION_MASK) {
> + case VERSIONS_PCB_TRANSMISSION_FIBER_10G:
> + versions->pcb_transmission_type = PCB_FIBER_10G;
> + break;
> +
> + case VERSIONS_PCB_TRANSMISSION_CAT_10G:
> + versions->pcb_transmission_type = PCB_CAT_10G;
> + break;
> +
> + case VERSIONS_PCB_TRANSMISSION_FIBER_3G:
> + versions->pcb_transmission_type = PCB_FIBER_3G;
> + break;
> +
> + case VERSIONS_PCB_TRANSMISSION_CAT_1G:
> + versions->pcb_transmission_type = PCB_CAT_1G;
> + break;
> +
> + }
>
> - FPGA_GET_REG(0, fpga_features, &fpga_features);
> - feature_osd = fpga_features & (1<<11);
> + versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
>
> - return feature_osd;
> + return 0;
> }
>
> -void ioep_fpga_print_info(unsigned int fpga)
> +static int get_features(unsigned int fpga, struct fpga_features *features)
> {
> - u16 versions;
> - u16 fpga_version;
> - u16 fpga_features;
> - unsigned unit_type;
> - unsigned unit_type_pcb_video;
> - unsigned feature_compression;
> - unsigned feature_osd;
> - unsigned feature_audio;
> - unsigned feature_sysclock;
> - unsigned feature_ramconfig;
> - unsigned feature_carrier_speed;
> - unsigned feature_carriers;
> - unsigned feature_video_channels;
> -
> - FPGA_GET_REG(fpga, versions, &versions);
> - FPGA_GET_REG(fpga, fpga_version, &fpga_version);
> - FPGA_GET_REG(fpga, fpga_features, &fpga_features);
> -
> - unit_type = (versions & 0xf000) >> 12;
> - unit_type_pcb_video = (versions & 0x01c0) >> 6;
> - feature_compression = (fpga_features & 0xe000) >> 13;
> - feature_osd = fpga_features & (1<<11);
> - feature_audio = (fpga_features & 0x0600) >> 9;
> - feature_sysclock = (fpga_features & 0x0180) >> 7;
> - feature_ramconfig = (fpga_features & 0x0060) >> 5;
> - feature_carrier_speed = fpga_features & (1<<4);
> - feature_carriers = (fpga_features & 0x000c) >> 2;
> - feature_video_channels = fpga_features & 0x0003;
> -
> - switch (unit_type) {
> - case UNITTYPE_MAIN_SERVER:
> - case UNITTYPE_MAIN_USER:
> - printf("Mainchannel");
> + enum {
> + FEATURE_SPDIF_RX = BIT(15),
> + FEATURE_SPDIF_TX = BIT(14),
> + FEATURE_PCM_RX = BIT(13),
> + FEATURE_PCM_TX = BIT(12),
> + FEATURE_RAM_MASK = GENMASK(11, 8),
> + FEATURE_RAM_DDR2_32BIT_295MBPS = 0x0 << 8,
> + FEATURE_RAM_DDR3_32BIT_590MBPS = 0x1 << 8,
> + FEATURE_RAM_DDR3_48BIT_590MBPS = 0x2 << 8,
> + FEATURE_RAM_DDR3_64BIT_1800MBPS = 0x3 << 8,
> + FEATURE_RAM_DDR3_48BIT_1800MBPS = 0x4 << 8,
> + FEATURE_CARRIER_SPEED_MASK = GENMASK(7, 6),
> + FEATURE_CARRIER_SPEED_1G = 0x0 << 6,
> + FEATURE_CARRIER_SPEED_2_5G = 0x1 << 6,
> + FEATURE_CARRIER_SPEED_10G = 0x2 << 6,
> + FEATURE_CARRIERS_MASK = GENMASK(5, 4),
> + FEATURE_CARRIERS_0 = 0x0 << 4,
> + FEATURE_CARRIERS_1 = 0x1 << 4,
> + FEATURE_CARRIERS_2 = 0x2 << 4,
> + FEATURE_CARRIERS_4 = 0x3 << 4,
> + FEATURE_USB2 = BIT(3),
> + FEATURE_VIDEOCHANNELS_MASK = GENMASK(2, 0),
> + FEATURE_VIDEOCHANNELS_0 = 0x0 << 0,
> + FEATURE_VIDEOCHANNELS_1 = 0x1 << 0,
> + FEATURE_VIDEOCHANNELS_1_1 = 0x2 << 0,
> + FEATURE_VIDEOCHANNELS_2 = 0x3 << 0,
> + };
> +
> + enum {
> + EXT_FEATURE_OSD = BIT(15),
> + EXT_FEATURE_ETHERNET = BIT(9),
> + EXT_FEATURE_INTERLACE = BIT(8),
> + EXT_FEATURE_RS232 = BIT(7),
> + EXT_FEATURE_COMPRESSION_PERF_MASK = GENMASK(6, 4),
> + EXT_FEATURE_COMPRESSION_PERF_1X = 0x0 << 4,
> + EXT_FEATURE_COMPRESSION_PERF_2X = 0x1 << 4,
> + EXT_FEATURE_COMPRESSION_PERF_4X = 0x2 << 4,
> + EXT_FEATURE_COMPRESSION_TYPE1 = BIT(0),
> + EXT_FEATURE_COMPRESSION_TYPE2 = BIT(1),
> + EXT_FEATURE_COMPRESSION_TYPE3 = BIT(2),
> + };
> +
> + u16 raw_features;
> + u16 raw_extended_features;
> +
> + memset(features, 0, sizeof(struct fpga_features));
> +
> + FPGA_GET_REG(fpga, fpga_features, &raw_features);
> + FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features);
> +
> + switch (raw_features & FEATURE_VIDEOCHANNELS_MASK) {
> + case FEATURE_VIDEOCHANNELS_0:
> + features->video_channels = 0;
> break;
>
> - case UNITTYPE_VIDEO_SERVER:
> - case UNITTYPE_VIDEO_USER:
> - printf("Videochannel");
> + case FEATURE_VIDEOCHANNELS_1:
> + features->video_channels = 1;
> break;
>
> - default:
> - printf("UnitType %d(not supported)", unit_type);
> + case FEATURE_VIDEOCHANNELS_1_1:
> + case FEATURE_VIDEOCHANNELS_2:
> + features->video_channels = 2;
> break;
> - }
> + };
>
> - switch (unit_type) {
> - case UNITTYPE_MAIN_SERVER:
> - case UNITTYPE_VIDEO_SERVER:
> - printf(" Server");
> - if (versions & (1<<4))
> - printf(" UC");
> + switch (raw_features & FEATURE_CARRIERS_MASK) {
> + case FEATURE_CARRIERS_0:
> + features->carriers = 0;
> break;
>
> - case UNITTYPE_MAIN_USER:
> - case UNITTYPE_VIDEO_USER:
> - printf(" User");
> + case FEATURE_CARRIERS_1:
> + features->carriers = 1;
> break;
>
> - default:
> + case FEATURE_CARRIERS_2:
> + features->carriers = 2;
> + break;
> +
> + case FEATURE_CARRIERS_4:
> + features->carriers = 4;
> break;
> }
>
> - if (versions & (1<<5))
> - printf(" Fiber");
> - else
> - printf(" CAT");
> + switch (raw_features & FEATURE_CARRIER_SPEED_MASK) {
> + case FEATURE_CARRIER_SPEED_1G:
> + features->carrier_speed = CARRIER_SPEED_1G;
> + break;
> + case FEATURE_CARRIER_SPEED_2_5G:
> + features->carrier_speed = CARRIER_SPEED_2_5G;
> + break;
> + case FEATURE_CARRIER_SPEED_10G:
> + features->carrier_speed = CARRIER_SPEED_10G;
> + break;
> + }
>
> - switch (unit_type_pcb_video) {
> - case UNITTYPEPCB_DVI:
> - printf(" DVI,");
> + switch (raw_features & FEATURE_RAM_MASK) {
> + case FEATURE_RAM_DDR2_32BIT_295MBPS:
> + features->ram_config = RAM_DDR2_32BIT_295MBPS;
> break;
>
> - case UNITTYPEPCB_DP_165:
> - printf(" DP 165MPix/s,");
> + case FEATURE_RAM_DDR3_32BIT_590MBPS:
> + features->ram_config = RAM_DDR3_32BIT_590MBPS;
> break;
>
> - case UNITTYPEPCB_DP_300:
> - printf(" DP 300MPix/s,");
> + case FEATURE_RAM_DDR3_48BIT_590MBPS:
> + features->ram_config = RAM_DDR3_48BIT_590MBPS;
> break;
>
> - case UNITTYPEPCB_HDMI:
> - printf(" HDMI,");
> + case FEATURE_RAM_DDR3_64BIT_1800MBPS:
> + features->ram_config = RAM_DDR3_64BIT_1800MBPS;
> + break;
> +
> + case FEATURE_RAM_DDR3_48BIT_1800MBPS:
> + features->ram_config = RAM_DDR3_48BIT_1800MBPS;
> break;
> }
>
> - printf(" FPGA V %d.%02d\n features:",
> - fpga_version / 100, fpga_version % 100);
> + features->pcm_tx = raw_features & FEATURE_PCM_TX;
> + features->pcm_rx = raw_features & FEATURE_PCM_RX;
> + features->spdif_tx = raw_features & FEATURE_SPDIF_TX;
> + features->spdif_rx = raw_features & FEATURE_SPDIF_RX;
> + features->usb2 = raw_features & FEATURE_USB2;
> + features->rs232 = raw_extended_features & EXT_FEATURE_RS232;
> + features->compression_type1 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE1;
> + features->compression_type2 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE2;
> + features->compression_type3 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE3;
> + features->interlace = raw_extended_features & EXT_FEATURE_INTERLACE;
> + features->osd = raw_extended_features & EXT_FEATURE_OSD;
> + features->compression_pipes = raw_extended_features & EXT_FEATURE_COMPRESSION_PERF_MASK;
> +
> + return 0;
> +}
> +
> +#else
> +
> +static int get_versions(unsigned int fpga, struct fpga_versions *versions)
> +{
> + enum {
> + /* HW version encoding is a mess, leave it for the moment */
> + VERSIONS_HW_VER_MASK = 0xf << 0,
> + VERSIONS_PIX_CLOCK_GEN_IDT8N3QV01 = BIT(4),
> + VERSIONS_SFP = BIT(5),
> + VERSIONS_VIDEO_MASK = 0x7 << 6,
> + VERSIONS_VIDEO_DVI = 0x0 << 6,
> + VERSIONS_VIDEO_DP_165 = 0x1 << 6,
> + VERSIONS_VIDEO_DP_300 = 0x2 << 6,
> + VERSIONS_VIDEO_HDMI = 0x3 << 6,
> + VERSIONS_UT_MASK = 0xf << 12,
> + VERSIONS_UT_MAIN_SERVER = 0x0 << 12,
> + VERSIONS_UT_MAIN_USER = 0x1 << 12,
> + VERSIONS_UT_VIDEO_SERVER = 0x2 << 12,
> + VERSIONS_UT_VIDEO_USER = 0x3 << 12,
> + };
> + u16 raw_versions;
> +
> + memset(versions, 0, sizeof(struct fpga_versions));
> +
> + FPGA_GET_REG(fpga, versions, &raw_versions);
> +
> + switch (raw_versions & VERSIONS_UT_MASK) {
> + case VERSIONS_UT_MAIN_SERVER:
> + versions->video_channel = false;
> + versions->con_side = false;
> + break;
> +
> + case VERSIONS_UT_MAIN_USER:
> + versions->video_channel = false;
> + versions->con_side = true;
> + break;
>
> + case VERSIONS_UT_VIDEO_SERVER:
> + versions->video_channel = true;
> + versions->con_side = false;
> + break;
>
> - switch (feature_compression) {
> - case COMPRESSION_NONE:
> - printf(" no compression");
> + case VERSIONS_UT_VIDEO_USER:
> + versions->video_channel = true;
> + versions->con_side = true;
> break;
>
> - case COMPRESSION_TYPE_1:
> - printf(" compression type1(delta)");
> + }
> +
> + switch (raw_versions & VERSIONS_VIDEO_MASK) {
> + case VERSIONS_VIDEO_DVI:
> + versions->pcb_video_type = PCB_DVI_SL;
> break;
>
> - case COMPRESSION_TYPE_1_2:
> - printf(" compression type1(delta), type2(inline)");
> + case VERSIONS_VIDEO_DP_165:
> + versions->pcb_video_type = PCB_DP_165MPIX;
> break;
>
> - case COMPRESSION_TYPE_1_2_3:
> - printf(" compression type1(delta), type2(inline), type3(intempo)");
> + case VERSIONS_VIDEO_DP_300:
> + versions->pcb_video_type = PCB_DP_300MPIX;
> break;
>
> - default:
> - printf(" compression %d(not supported)", feature_compression);
> + case VERSIONS_VIDEO_HDMI:
> + versions->pcb_video_type = PCB_HDMI;
> break;
> }
>
> - printf(", %sosd", feature_osd ? "" : "no ");
> + versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
>
> - switch (feature_audio) {
> - case AUDIO_NONE:
> - printf(", no audio");
> + if (raw_versions & VERSIONS_SFP)
> + versions->pcb_transmission_type = PCB_FIBER_3G;
> + else
> + versions->pcb_transmission_type = PCB_CAT_1G;
> +
> + return 0;
> +}
> +
> +static int get_features(unsigned int fpga, struct fpga_features *features)
> +{
> + enum {
> + FEATURE_CARRIER_SPEED_2_5 = BIT(4),
> + FEATURE_RAM_MASK = 0x7 << 5,
> + FEATURE_RAM_DDR2_32BIT = 0x0 << 5,
> + FEATURE_RAM_DDR3_32BIT = 0x1 << 5,
> + FEATURE_RAM_DDR3_48BIT = 0x2 << 5,
> + FEATURE_PCM_AUDIO_TX = BIT(9),
> + FEATURE_PCM_AUDIO_RX = BIT(10),
> + FEATURE_OSD = BIT(11),
> + FEATURE_USB20 = BIT(12),
> + FEATURE_COMPRESSION_MASK = 7 << 13,
> + FEATURE_COMPRESSION_TYPE1 = 0x1 << 13,
> + FEATURE_COMPRESSION_TYPE1_TYPE2 = 0x3 << 13,
> + FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3 = 0x7 << 13,
> + };
> +
> + enum {
> + EXTENDED_FEATURE_SPDIF_AUDIO_TX = BIT(0),
> + EXTENDED_FEATURE_SPDIF_AUDIO_RX = BIT(1),
> + EXTENDED_FEATURE_RS232 = BIT(2),
> + EXTENDED_FEATURE_COMPRESSION_PIPES = BIT(3),
> + EXTENDED_FEATURE_INTERLACE = BIT(4),
> + };
> +
> + u16 raw_features;
> + u16 raw_extended_features;
> +
> + memset(features, 0, sizeof(struct fpga_features));
> +
> + FPGA_GET_REG(fpga, fpga_features, &raw_features);
> + FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features);
> +
> + features->video_channels = raw_features & 0x3;
> + features->carriers = (raw_features >> 2) & 0x3;
> +
> + features->carrier_speed = (raw_features & FEATURE_CARRIER_SPEED_2_5)
> + ? CARRIER_SPEED_2_5G : CARRIER_SPEED_1G;
> +
> + switch (raw_features & FEATURE_RAM_MASK) {
> + case FEATURE_RAM_DDR2_32BIT:
> + features->ram_config = RAM_DDR2_32BIT_295MBPS;
> break;
>
> - case AUDIO_TX:
> - printf(", audio tx");
> + case FEATURE_RAM_DDR3_32BIT:
> + features->ram_config = RAM_DDR3_32BIT_590MBPS;
> break;
>
> - case AUDIO_RX:
> - printf(", audio rx");
> + case FEATURE_RAM_DDR3_48BIT:
> + features->ram_config = RAM_DDR3_48BIT_590MBPS;
> break;
> + }
>
> - case AUDIO_RXTX:
> - printf(", audio rx+tx");
> + features->pcm_tx = raw_features & FEATURE_PCM_AUDIO_TX;
> + features->pcm_rx = raw_features & FEATURE_PCM_AUDIO_RX;
> + features->spdif_tx = raw_extended_features & EXTENDED_FEATURE_SPDIF_AUDIO_TX;
> + features->spdif_rx = raw_extended_features & EXTENDED_FEATURE_SPDIF_AUDIO_RX;
> +
> + features->usb2 = raw_features & FEATURE_USB20;
> + features->rs232 = raw_extended_features & EXTENDED_FEATURE_RS232;
> +
> + features->compression_type1 = false;
> + features->compression_type2 = false;
> + features->compression_type3 = false;
> + switch (raw_features & FEATURE_COMPRESSION_MASK) {
> + case FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3:
> + features->compression_type3 = true;
> + case FEATURE_COMPRESSION_TYPE1_TYPE2:
> + features->compression_type2 = true;
> + case FEATURE_COMPRESSION_TYPE1:
> + features->compression_type1 = true;
> break;
> + }
> +
> + features->interlace = raw_extended_features & EXTENDED_FEATURE_INTERLACE;
> + features->osd = raw_features & FEATURE_OSD;
> + features->compression_pipes = raw_extended_features & EXTENDED_FEATURE_COMPRESSION_PIPES;
>
> - default:
> - printf(", audio %d(not supported)", feature_audio);
> + return 0;
> +}
> +
> +#endif
> +
> +bool ioep_fpga_has_osd(unsigned int fpga)
> +{
> + struct fpga_features features;
> +
> + get_features(fpga, &features);
> +
> + return features.osd;
> +}
> +
> +void ioep_fpga_print_info(unsigned int fpga)
> +{
> + u16 fpga_version;
> + struct fpga_versions versions;
> + struct fpga_features features;
> +
> + FPGA_GET_REG(fpga, fpga_version, &fpga_version);
> + get_versions(fpga, &versions);
> + get_features(fpga, &features);
> +
> + if (versions.video_channel)
> + printf("Videochannel");
> + else
> + printf("Mainchannel");
> +
> + if (versions.con_side)
> + printf(" User");
> + else
> + printf(" Server");
> +
> +// FIXME
> +#if 0
> + if (versions & (1<<4))
> + printf(" UC");
> +#endif
> +
> + switch(versions.pcb_transmission_type) {
> + case PCB_CAT_1G:
> + case PCB_CAT_10G:
> + printf(" CAT");
> + break;
> + case PCB_FIBER_3G:
> + case PCB_FIBER_10G:
> + printf(" Fiber");
> + break;
> + };
> +
> + switch (versions.pcb_video_type) {
> + case PCB_DVI_SL:
> + printf(" DVI,");
> + break;
> + case PCB_DP_165MPIX:
> + printf(" DP 165MPix/s,");
> + break;
> + case PCB_DP_300MPIX:
> + printf(" DP 300MPix/s,");
> + break;
> + case PCB_HDMI:
> + printf(" HDMI,");
> + break;
> + case PCB_DP_1_2:
> + printf(" DP 1.2,");
> + break;
> + case PCB_HDMI_2_0:
> + printf(" HDMI 2.0,");
> break;
> }
>
> + printf(" FPGA V %d.%02d\n features: ",
> + fpga_version / 100, fpga_version % 100);
> +
> + if (!features.compression_type1 &&
> + !features.compression_type2 &&
> + !features.compression_type3)
> + printf("no compression, ");
> +
> + if (features.compression_type1)
> + printf("type1-deltacompression, ");
> +
> + if (features.compression_type2)
> + printf("type2-inlinecompression, ");
> +
> + if (features.compression_type3)
> + printf("type3-intempocompression, ");
> +
> + printf("%sosd", features.osd ? "" : "no ");
> +
> + if (features.pcm_rx && features.pcm_tx)
> + printf(", pcm rx+tx");
> + else if(features.pcm_rx)
> + printf(", pcm rx");
> + else if(features.pcm_tx)
> + printf(", pcm tx");
> +
> + if (features.spdif_rx && features.spdif_tx)
> + printf(", spdif rx+tx");
> + else if(features.spdif_rx)
> + printf(", spdif rx");
> + else if(features.spdif_tx)
> + printf(", spdif tx");
> +
> puts(",\n ");
>
> - switch (feature_sysclock) {
> + switch (features.sysclock) {
> case SYSCLK_147456:
> printf("clock 147.456 MHz");
> break;
> -
> - default:
> - printf("clock %d(not supported)", feature_sysclock);
> - break;
> }
>
> - switch (feature_ramconfig) {
> - case RAM_DDR2_32:
> + switch (features.ram_config) {
> + case RAM_DDR2_32BIT_295MBPS:
> printf(", RAM 32 bit DDR2");
> break;
> -
> - case RAM_DDR3_32:
> + case RAM_DDR3_32BIT_590MBPS:
> printf(", RAM 32 bit DDR3");
> break;
> -
> - case RAM_DDR3_48:
> + case RAM_DDR3_48BIT_590MBPS:
> + case RAM_DDR3_48BIT_1800MBPS:
> printf(", RAM 48 bit DDR3");
> break;
> -
> - default:
> - printf(", RAM %d(not supported)", feature_ramconfig);
> + case RAM_DDR3_64BIT_1800MBPS:
> + printf(", RAM 64 bit DDR3");
> break;
> }
>
> - printf(", %d carrier(s) %s", feature_carriers,
> - feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
> + printf(", %d carrier(s)", features.carriers);
> +
> + switch(features.carrier_speed) {
> + case CARRIER_SPEED_1G:
> + printf(", 1Gbit/s");
> + break;
> + case CARRIER_SPEED_3G:
> + printf(", 3Gbit/s");
> + break;
> + case CARRIER_SPEED_10G:
> + printf(", 10Gbit/s");
> + break;
> + }
>
> - printf(", %d video channel(s)\n", feature_video_channels);
> + printf(", %d video channel(s)\n", features.video_channels);
> }
>
> #endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
> diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig
> index 80ac1a0f8a..79d0dc9829 100644
> --- a/board/gdsys/mpc8308/Kconfig
> +++ b/board/gdsys/mpc8308/Kconfig
> @@ -55,6 +55,25 @@ config GDSYS_LEGACY_DRIVERS
>
> endif
>
> +if TARGET_GAZERBEAM
> +
> +config SYS_BOARD
> + default "mpc8308"
> +
> +config SYS_VENDOR
> + default "gdsys"
> +
> +config SYS_CONFIG_NAME
> + default "gazerbeam"
> +
> +config SYS_FPGA1_BASE
> + default E0700000
> +
> +config SYS_FPGA1_SIZE
> + default 1
> +
> +endif
> +
> choice
> prompt "FPGA flavor selection"
>
> diff --git a/board/gdsys/mpc8308/MAINTAINERS b/board/gdsys/mpc8308/MAINTAINERS
> index 3895b01732..a986ae3664 100644
> --- a/board/gdsys/mpc8308/MAINTAINERS
> +++ b/board/gdsys/mpc8308/MAINTAINERS
> @@ -6,5 +6,7 @@ F: include/configs/hrcon.h
> F: configs/hrcon_defconfig
> F: configs/hrcon_dh_defconfig
> F: include/configs/strider.h
> +F: configs/strider_defconfig
> F: configs/strider_cpu_defconfig
> F: configs/strider_con_defconfig
> +F: configs/gazerbeam_defconfig
> diff --git a/board/gdsys/mpc8308/Makefile b/board/gdsys/mpc8308/Makefile
> index 42702fb967..bafb9beaaf 100644
> --- a/board/gdsys/mpc8308/Makefile
> +++ b/board/gdsys/mpc8308/Makefile
> @@ -8,3 +8,4 @@
> obj-y := mpc8308.o sdram.o
> obj-$(CONFIG_HRCON) += hrcon.o
> obj-$(CONFIG_STRIDER) += strider.o
> +obj-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.o
> diff --git a/board/gdsys/mpc8308/gazerbeam.c b/board/gdsys/mpc8308/gazerbeam.c
> new file mode 100644
> index 0000000000..a86333d92c
> --- /dev/null
> +++ b/board/gdsys/mpc8308/gazerbeam.c
> @@ -0,0 +1,332 @@
> +/*
> + * (C) Copyright 2015
> + * Dirk Eibach, Guntermann & Drunck GmbH, eibach at gdsys.de
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <dm/device-internal.h>
> +#include <dm/uclass-internal.h>
> +#include <fsl_esdhc.h>
> +#include <gdsys_rxaui_ctrl.h>
> +#include <marvell-phy.h>
> +#include <miiphy.h>
> +#include <tpm.h>
> +#include <i2c.h>
> +#include <asm/fsl_mpc83xx_serdes.h>
> +#include <asm/gpio.h>
> +
> +#include "../../../drivers/net/phy/mv88x2.h"
> +#include "../common/ihs_mdio.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct ihs_mdio_info ihs_mdio_info[] = {
> + { .fpga = NULL, .name = "ihs0", .clause45 = true, .base = 0x58 },
> + { .fpga = NULL, .name = "ihs1", .clause45 = true, .base = 0x58 },
> +};
> +
> +int child_find_by_name(struct udevice *parent, const char *dev_name,
> + struct udevice **child)
Can we add (in separate patch with test) dev_find_child_by_name() in
the dm core code?
> +{
> + struct udevice *dev = NULL;
> +
> + for (device_find_first_child(parent, &dev);
> + dev;
> + device_find_next_child(&dev)) {
> + if (!strncmp(dev->name, dev_name, strlen(dev_name))) {
> + *child = dev;
> + return 0;
> + }
> + }
> +
> + return -1;
> +}
> +
> +int request_gpio_by_dev(struct gpio_desc *gpio, struct udevice *gpio_dev,
> + uint offset, char *gpio_name)
> +{
> + gpio->dev = gpio_dev;
> + gpio->offset = offset;
> + gpio->flags = 0;
> +
> + return dm_gpio_request(gpio, gpio_name);
> +}
> +
> +void determine_board_type(struct of_board_fixup_data *data)
> +{
> + struct udevice *i2c_bus;
> + struct udevice *dummy;
> + struct udevice *gpio_dev = NULL;
> + struct gpio_desc gpio;
> + char name[16];
> +
> + uclass_get_device_by_name(UCLASS_I2C, "i2c at 3100", &i2c_bus);
Can you use an alias to find this and get by seq? Or have a property
somewhere which points to this as a phandle?
> +
> + if (!i2c_bus) {
> + puts("Could not get I2C bus\n");
> + return;
> + }
> +
> + data->mc2 = !dm_i2c_probe(i2c_bus, 0x20, 0, &dummy);
> + data->mc4 = !dm_i2c_probe(i2c_bus, 0x22, 0, &dummy);
> +
> + if (data->mc2 && data->mc4) {
> + puts("Board hardware configuration inconsistent.");
> + return;
> + }
> +
> + snprintf(name, sizeof(name), "pca9698@%x", data->mc4 ? 0x22 : 0x20);
> +
> + if (child_find_by_name(i2c_bus, name, &gpio_dev)) {
> + printf("Could not find child %s of device %s\n", name,
> + i2c_bus->name);
> + return;
> + }
> +
> + device_probe(gpio_dev);
Let's have device_get_child_by_name() also. We should not explicitly
probe outside DM code if possible.
> +
> + if (!data->mc4) {
> + if (!request_gpio_by_dev(&gpio, gpio_dev, 0, "var-mc_sc"))
Can you have this GPIO in the device tree so you can use
gpio_request_by_name() from a driver? What is this GPIO for?
> + data->mc2 = !dm_gpio_get_value(&gpio);
> + else
> + puts("Could not query var-mc_sc GPIO.\n");
> +
> + dm_gpio_free(gpio_dev, &gpio);
> + }
> +
> + if (!request_gpio_by_dev(&gpio, gpio_dev, 11, "var-con"))
> + data->var_con = dm_gpio_get_value(&gpio);
> + else
> + puts("Could not query var-con GPIO.\n");
> +
> + dm_gpio_free(gpio_dev, &gpio);
> +}
> +
> +int board_fix_fdt_get_info(void)
> +{
> + struct of_board_fixup_data data;
> +
> + determine_board_type(&data);
> +
> + gd->board_fixup_data.var_con = data.var_con;
> + gd->board_fixup_data.mc2 = data.mc2;
> + gd->board_fixup_data.mc4 = data.mc4;
> +
> + return 0;
> +}
> +
> +int fdt_disable_by_ofname(void *rw_fdt_blob, char *ofname)
> +{
> + int offset = fdt_path_offset(rw_fdt_blob, ofname);
> +
> + return fdt_status_disabled(rw_fdt_blob, offset);
> +}
> +
> +int board_fix_fdt_change(void *rw_fdt_blob)
> +{
> + struct of_board_fixup_data data = gd->board_fixup_data;
> +
> + if (!data.mc4) {
> + fdt_disable_by_ofname(rw_fdt_blob,
> + "/localbus at e0005000/iocon_uart at 2,0");
> + fdt_disable_by_ofname(rw_fdt_blob, "/fpga1bus");
> + }
> +
> + if (!data.mc2 || !data.var_con) {
> + fdt_disable_by_ofname(rw_fdt_blob, "/fpga0bus/fpga0_video1");
> + fdt_disable_by_ofname(rw_fdt_blob, "/fpga0bus/fpga0_iic_video1");
> + fdt_disable_by_ofname(rw_fdt_blob, "/fpga0bus/fpga0_axi_video1");
> + }
> +
> + if (!data.var_con) {
> + fdt_disable_by_ofname(rw_fdt_blob, "/fpga0bus/fpga0_video0");
> + fdt_disable_by_ofname(rw_fdt_blob, "/fpga0bus/fpga0_iic_video0");
> + fdt_disable_by_ofname(rw_fdt_blob, "/fpga0bus/fpga0_axi_video0");
> + }
> +
> + return 0;
> +}
> +
> +int checkboard(void)
> +{
> + struct of_board_fixup_data data = gd->board_fixup_data;
> + char *s = getenv("serial#");
> +
> + puts("Board: Gazerbeam ");
> + printf("%s ", data.mc4 ? "MC4" : data.mc2 ? "MC2" : "SC");
> + printf("%s", data.var_con ? "CON" : "CPU");
> +
> + if (s) {
> + puts(", serial# ");
> + puts(s);
> + }
> +
> + puts("\n");
> +
> + return 0;
> +}
> +
> +int last_stage_init(void)
> +{
> + uint fpga_hw_rev = 0;
> + uint k = 0;
> + struct udevice *fpga;
> + struct udevice *rxaui;
> + struct udevice *i2c_bus;
> + struct udevice *gpio_dev;
> + char name[16];
> +
> + uclass_get_device_by_name(UCLASS_I2C, "i2c at 3000", &i2c_bus);
> +
> + if (child_find_by_name(i2c_bus, "pca9698 at 20", &gpio_dev)) {
> + printf("Could not find child %s of device %s\n", name,
> + i2c_bus->name);
> + return -1;
> + }
> +
> + device_probe(gpio_dev);
> +
> + for (k = 0; k < 4; ++k) {
> + struct gpio_desc gpio;
> +
> + snprintf(name, sizeof(name), "fpga_hw_rev%d", k);
> +
> + if (!request_gpio_by_dev(&gpio, gpio_dev, 12 + k, name))
> + fpga_hw_rev |= dm_gpio_get_value(&gpio) ? BIT(k) : 0;
> + }
> +
> + setenv_ulong("fpga_hw_rev", fpga_hw_rev);
Can we use gpio_request_list_by_name() and dm_gpio_get_values_as_int() ?
> +
> + if (tpm_init() || tpm_startup(TPM_ST_CLEAR) ||
> + tpm_continue_self_test()) {
> + printf("TPM init failed\n");
> + }
> +
> + if (fpga_hw_rev >= 4) {
> + for (uclass_find_first_device(UCLASS_RXAUI_CTRL, &rxaui);
> + rxaui;
> + uclass_find_next_device(&rxaui)) {
> + rxaui_disable_polarity_inversion(rxaui);
> + }
> + }
> +
> + for (uclass_find_first_device(UCLASS_IHS_FPGA, &fpga);
> + fpga;
> + uclass_find_next_device(&fpga)) {
Can you use uclass_first_next_device() since it does the probing for you.
> + struct mii_dev *bus;
> +
> + device_probe(fpga);
> +
> + if (fpga->seq < 0)
> + continue;
What is this checking for?
> +
> + ihs_mdio_info[fpga->seq].fpga = fpga;
> +
> + ihs_mdio_init(&ihs_mdio_info[fpga->seq]);
> + bus = miiphy_get_dev_by_name(fpga->seq ? "ihs1" : "ihs0");
> + if (bus) {
> + struct phy_device *phydev;
> +
> + phydev = phy_find_by_mask_c45(bus, 1,
> + PHY_INTERFACE_MODE_XGMII);
> + if (phydev)
> + phy_config(phydev);
> + }
> + }
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_FSL_ESDHC
> +int board_mmc_init(bd_t *bd)
> +{
> + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
> + sysconf83xx_t *sysconf = &immr->sysconf;
> +
> + /* Enable cache snooping in eSDHC system configuration register */
> + out_be32(&sysconf->sdhccr, 0x02000000);
> +
> + return fsl_esdhc_mmc_init(bd);
> +}
> +#endif
> +
> +static struct pci_region pcie_regions_0[] = {
> + {
> + .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
> + .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
> + .size = CONFIG_SYS_PCIE1_MEM_SIZE,
> + .flags = PCI_REGION_MEM,
> + },
> + {
> + .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
> + .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
> + .size = CONFIG_SYS_PCIE1_IO_SIZE,
> + .flags = PCI_REGION_IO,
> + },
> +};
> +
> +void pci_init_board(void)
> +{
> + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
> + sysconf83xx_t *sysconf = &immr->sysconf;
> + law83xx_t *pcie_law = sysconf->pcielaw;
> + struct pci_region *pcie_reg[] = { pcie_regions_0 };
> +
> + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
> + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
> +
> + /* Deassert the resets in the control register */
> + out_be32(&sysconf->pecr1, 0xE0008000);
> + udelay(2000);
> +
> + /* Configure PCI Express Local Access Windows */
> + out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
> + out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
> +
> + mpc83xx_pcie_init(1, pcie_reg);
> +}
> +
> +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
> +{
> + info->portwidth = FLASH_CFI_16BIT;
> + info->chipwidth = FLASH_CFI_BY16;
> + info->interface = FLASH_CFI_X16;
> + return 1;
> +}
> +
> +#if defined(CONFIG_OF_BOARD_SETUP)
> +int ft_board_setup(void *blob, bd_t *bd)
> +{
> + ft_cpu_setup(blob, bd);
> + fsl_fdt_fixup_dr_usb(blob, bd);
> + fdt_fixup_esdhc(blob, bd);
> +
> + return 0;
> +}
> +#endif
> +
> +int board_m88e1510_config(struct phy_device *phydev)
> +{
> + /* Select page 3 */
> + phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
> +
> + /* Configure LEDs */
> + m88e1518_phy_writebits(phydev, 16, 0, 4, 4);
> + m88e1518_phy_writebits(phydev, 16, 4, 4, 8);
> + m88e1518_phy_writebits(phydev, 16, 8, 4, 0);
> +
> + /* Reset page selection */
> + phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
> +
> + return 0;
> +}
> +
> +int board_mv88x2_config(struct mv88x2_config_data *data)
> +{
> + data->sfi_pol = (getenv_ulong("fpga_hw_rev", 10, 0) < 4) ? 0x0f03 : 0;
> +
> + return 0;
> +}
> diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig
> new file mode 100644
> index 0000000000..4fc92ea19b
> --- /dev/null
> +++ b/configs/gazerbeam_defconfig
> @@ -0,0 +1,76 @@
> +CONFIG_PPC=y
> +CONFIG_SYS_MALLOC_F_LEN=0x600
> +CONFIG_IDENT_STRING=" gazerbeam 0.01"
> +CONFIG_MPC83xx=y
> +CONFIG_TARGET_GAZERBEAM=y
> +CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM=y
> +CONFIG_CMD_IOLOOP=y
> +CONFIG_DEFAULT_DEVICE_TREE="gazerbeam"
> +CONFIG_FIT=y
> +CONFIG_FIT_SIGNATURE=y
> +CONFIG_FIT_VERBOSE=y
> +CONFIG_OF_BOARD_SETUP=y
> +CONFIG_OF_STDOUT_VIA_ALIAS=y
> +CONFIG_BOOTDELAY=5
> +CONFIG_SYS_CONSOLE_INFO_QUIET=y
> +# CONFIG_DISPLAY_BOARDINFO is not set
> +CONFIG_HUSH_PARSER=y
> +CONFIG_AUTOBOOT_KEYED=y
> +CONFIG_AUTOBOOT_STOP_STR=" "
> +CONFIG_CMD_MEMTEST=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_I2C=y
> +# CONFIG_CMD_FPGA is not set
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_IHS_FPGA=y
> +CONFIG_CMD_IHS_AXI=y
> +# CONFIG_CMD_SETEXPR is not set
> +# CONFIG_CMD_NFS is not set
> +CONFIG_CMD_MII=y
> +CONFIG_CMD_MII_DRIVER=y
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_HASH=y
> +CONFIG_CMD_TPM=y
> +CONFIG_CMD_EXT2=y
> +CONFIG_DOS_PARTITION=y
> +CONFIG_OF_CONTROL=y
> +CONFIG_OF_BOARD_FIXUP=y
> +CONFIG_OF_EMBED=y
> +CONFIG_DM=y
> +CONFIG_CLK=y
> +CONFIG_ICS8N3QV01=y
> +CONFIG_DM_GPIO=y
> +CONFIG_DM_PCA953X=y
> +CONFIG_MPC8XXX_GPIO=y
> +CONFIG_DM_I2C=y
> +CONFIG_SYS_I2C_FSL=y
> +CONFIG_SYS_I2C_IHS=y
> +CONFIG_MISC=y
> +CONFIG_IHS_FPGA=y
> +CONFIG_IHS_AXI=y
> +CONFIG_IHS_VIDEO_OUT=y
> +CONFIG_GDSYS_RXAUI_CTRL=y
> +CONFIG_GDSYS_IOEP=y
> +CONFIG_MTD=y
> +CONFIG_MTD_NOR_FLASH=y
> +CONFIG_CFI_FLASH=y
> +CONFIG_PHYLIB=y
> +CONFIG_PHYLIB_10G=y
> +CONFIG_PHY_MARVELL=y
> +CONFIG_BOARD_M88E1510_CONFIG=y
> +CONFIG_PHY_MV88X2=y
> +CONFIG_BOARD_MV88X2_CONFIG=y
> +CONFIG_MV88X2_DEBUG_REGS=y
> +CONFIG_MV88X2_LINE_10GBASE_R=y
> +CONFIG_MV88X2_HOST_10GBASE_X2=y
> +CONFIG_MV88X2_X2_DISPARITY=y
> +CONFIG_MV88X2_LED0_SOLID=6
> +CONFIG_MV88X2_LED1_SOLID=6
> +CONFIG_MV88X2_HOST_LANE_MUX_2_PORT=0x0800
> +CONFIG_DM_SERIAL=y
> +CONFIG_SYS_NS16550=y
> +CONFIG_TPM_ATMEL_TWI=y
> +CONFIG_TPM_AUTH_SESSIONS=y
> +CONFIG_TRANSMITTER=y
> +CONFIG_LOGICORE_DP_TX=y
> +CONFIG_TPM=y
> diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h
> new file mode 100644
> index 0000000000..a8d0474771
> --- /dev/null
> +++ b/include/configs/gazerbeam.h
> @@ -0,0 +1,484 @@
> +/*
> + * (C) Copyright 2015
> + * Dirk Eibach, Guntermann & Drunck GmbH, eibach at gdsys.de
> + *
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +/*
> + * High Level Configuration Options
> + */
> +#define CONFIG_E300 1 /* E300 family */
> +#define CONFIG_MPC83xx 1 /* MPC83xx family */
> +#define CONFIG_MPC830x 1 /* MPC830x family */
> +#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
Can you drop the '1' in these?
> +
> +#define CONFIG_SYS_TEXT_BASE 0xFE000000
> +
> +#define CONFIG_LAST_STAGE_INIT
> +#define CONFIG_DISPLAY_BOARDINFO_LATE
> +
> +#define CONFIG_FSL_ESDHC
> +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
> +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
> +
> +#define CONFIG_SYS_ALT_MEMTEST
> +
> +/*
> + * System Clock Setup
> + */
> +#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
> +#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
> +
> +/*
> + * Hardware Reset Configuration Word
> + * if CLKIN is 66.66MHz, then
> + * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
> + * We choose the A type silicon as default, so the core is 400Mhz.
> + */
> +#define CONFIG_SYS_HRCW_LOW (\
> + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
> + HRCWL_DDR_TO_SCB_CLK_2X1 |\
> + HRCWL_SVCOD_DIV_2 |\
> + HRCWL_CSB_TO_CLKIN_4X1 |\
> + HRCWL_CORE_TO_CSB_3X1)
Seems like this should be in the DT instead of a CONFIG. TBD for later?
> +/*
> + * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
> + * in 8308's HRCWH according to the manual, but original Freescale's
> + * code has them and I've expirienced some problems using the board
> + * with BDI3000 attached when I've tried to set these bits to zero
> + * (UART doesn't work after the 'reset run' command).
> + */
> +#define CONFIG_SYS_HRCW_HIGH (\
> + HRCWH_PCI_HOST |\
> + HRCWH_PCI1_ARBITER_ENABLE |\
> + HRCWH_CORE_ENABLE |\
> + HRCWH_FROM_0XFFF00100 |\
> + HRCWH_BOOTSEQ_DISABLE |\
> + HRCWH_SW_WATCHDOG_DISABLE |\
> + HRCWH_ROM_LOC_LOCAL_16BIT |\
> + HRCWH_RL_EXT_LEGACY |\
> + HRCWH_TSEC1M_IN_RGMII |\
> + HRCWH_TSEC2M_IN_RGMII |\
> + HRCWH_BIG_ENDIAN)
> +
> +/*
> + * System IO Config
> + */
> + #define CONFIG_SYS_SICRH (\
> + SICRH_ESDHC_A_SD |\
> + SICRH_ESDHC_B_SD |\
> + SICRH_ESDHC_C_SD |\
> + SICRH_GPIO_A_TSEC2 |\
> + SICRH_GPIO_B_TSEC2_GTX_CLK125 |\
> + SICRH_IEEE1588_A_GPIO |\
> + SICRH_USB |\
> + SICRH_GTM_GPIO |\
> + SICRH_IEEE1588_B_GPIO |\
> + SICRH_ETSEC2_GPIO |\
> + SICRH_GPIOSEL_1 |\
> + SICRH_TMROBI_V3P3 |\
> + SICRH_TSOBI1_V2P5 |\
> + SICRH_TSOBI2_V2P5) /* 0x01b7f103 */
> + #define CONFIG_SYS_SICRL (\
> + SICRL_SPI_PF0 |\
> + SICRL_UART_PF0 |\
> + SICRL_IRQ_PF0 |\
> + SICRL_I2C2_PF0 |\
> + SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */
> +
> +/*
> + * IMMR new address
> + */
> +#define CONFIG_SYS_IMMR 0xE0000000
> +
> +/*
> + * SERDES
> + */
> +#define CONFIG_FSL_SERDES
> +#define CONFIG_FSL_SERDES1 0xe3000
> +
> +/*
> + * Arbiter Setup
> + */
> +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
> +#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
> +#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
> +
> +/*
> + * DDR Setup
> + */
> +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
> +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
> +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
> +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
> +#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
> + | DDRCDR_PZ_LOZ \
> + | DDRCDR_NZ_LOZ \
> + | DDRCDR_ODT \
> + | DDRCDR_Q_DRN)
> + /* 0x7b880001 */
> +/*
> + * Manually set up DDR parameters
> + * consist of one chip NT5TU64M16HG from NANYA
> + */
> +
> +#define CONFIG_SYS_DDR_SIZE 128 /* MB */
> +
> +#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
> +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
> + | CSCONFIG_ODT_RD_NEVER \
> + | CSCONFIG_ODT_WR_ONLY_CURRENT \
> + | CSCONFIG_BANK_BIT_3 \
> + | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
> + /* 0x80010102 */
> +#define CONFIG_SYS_DDR_TIMING_3 0
> +#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
> + | (0 << TIMING_CFG0_WRT_SHIFT) \
> + | (0 << TIMING_CFG0_RRT_SHIFT) \
> + | (0 << TIMING_CFG0_WWT_SHIFT) \
> + | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
> + | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
> + | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
> + | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
> + /* 0x00260802 */
> +#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
> + | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
> + | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
> + | (7 << TIMING_CFG1_CASLAT_SHIFT) \
> + | (9 << TIMING_CFG1_REFREC_SHIFT) \
> + | (2 << TIMING_CFG1_WRREC_SHIFT) \
> + | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
> + | (2 << TIMING_CFG1_WRTORD_SHIFT))
> + /* 0x26279222 */
> +#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
> + | (4 << TIMING_CFG2_CPO_SHIFT) \
> + | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
> + | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
> + | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
> + | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
> + | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
> + /* 0x021848c5 */
> +#define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
> + | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
> + /* 0x08240100 */
> +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
> + | SDRAM_CFG_SDRAM_TYPE_DDR2 \
> + | SDRAM_CFG_DBW_16)
> + /* 0x43100000 */
> +
> +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
> +#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
> + | (0x0242 << SDRAM_MODE_SD_SHIFT))
> + /* ODT 150ohm CL=4, AL=0 on SDRAM */
> +#define CONFIG_SYS_DDR_MODE2 0x00000000
I think this should all be a UCLASS_RAM driver with DT configuration.
Too many CONFIGs :-)
> +
> +/*
> + * Memory test
> + */
> +#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
> +#define CONFIG_SYS_MEMTEST_END 0x07f00000
> +
> +/*
> + * The reserved memory
> + */
> +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
> +
> +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
> +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
> +
> +/*
> + * Initial RAM Base Address Setup
> + */
> +#define CONFIG_SYS_INIT_RAM_LOCK 1
> +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
> +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
> +#define CONFIG_SYS_GBL_DATA_OFFSET \
> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +
> +/*
> + * Local Bus Configuration & Clock Setup
> + */
> +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
> +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
> +#define CONFIG_SYS_LBC_LBCR 0x00040000
> +
> +/*
> + * FLASH on the Local Bus
> + */
> +#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
> +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
> +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
> +#define CONFIG_FLASH_CFI_LEGACY
> +#define CONFIG_SYS_FLASH_LEGACY_512Kx16
> +
> +#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
> +#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
> +#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
> +
> +/* Window base at flash base */
> +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
> +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
> +
> +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
> + | BR_PS_16 /* 16 bit port */ \
> + | BR_MS_GPCM /* MSEL = GPCM */ \
> + | BR_V) /* valid */
> +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
> + | OR_UPM_XAM \
> + | OR_GPCM_CSNT \
> + | OR_GPCM_ACS_DIV2 \
> + | OR_GPCM_XACS \
> + | OR_GPCM_SCY_15 \
> + | OR_GPCM_TRLX_SET \
> + | OR_GPCM_EHTR_SET)
> +
> +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
> +#define CONFIG_SYS_MAX_FLASH_SECT 135
> +
> +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
> +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
> +
> +/* Window base at FPGA base */
> +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE
> +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB)
> +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_FPGA1_BASE
> +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_1MB)
> +
> +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \
> + | BR_PS_16 /* 16 bit port */ \
> + | BR_MS_GPCM /* MSEL = GPCM */ \
> + | BR_V) /* valid */
> +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
> + | OR_UPM_XAM \
> + | OR_GPCM_CSNT \
> + | OR_GPCM_SCY_5 \
> + | OR_GPCM_TRLX_CLEAR \
> + | OR_GPCM_EHTR_CLEAR)
> +
> +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_FPGA1_BASE \
> + | BR_PS_16 /* 16 bit port */ \
> + | BR_MS_GPCM /* MSEL = GPCM */ \
> + | BR_V) /* valid */
> +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA1_SIZE) \
> + | OR_UPM_XAM \
> + | OR_GPCM_CSNT \
> + | OR_GPCM_SCY_5 \
> + | OR_GPCM_TRLX_CLEAR \
> + | OR_GPCM_EHTR_CLEAR)
Put this config in the DT.
> +
> +#define CONFIG_SYS_FPGA_COUNT 2
Should not be needed with DT.
> +
> +#define CONFIG_SYS_FPGA_PTR { \
> + (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
> + (struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
Get base address from DT.
> +
> +#define CONFIG_SYS_FPGA_NO_RFL_HI
> +
> +#define CONFIG_SYS_BAUDRATE_TABLE \
> + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
> +
> +#define CONFIG_SYS_ICS8N3QV01_I2C { 3, 6, 4, 7 }
> +
> +/*
> + * General PCI
> + * Addresses are mapped 1-1.
> + */
> +#define CONFIG_SYS_PCIE1_BASE 0xA0000000
> +#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
> +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
> +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
> +#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
> +#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
> +#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
> +#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
> +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
PCI driver for DM?
> +
> +/* enable PCIE clock */
> +#define CONFIG_SYS_SCCR_PCIEXP1CM 1
> +
> +#define CONFIG_PCI_INDIRECT_BRIDGE
> +#define CONFIG_PCIE
> +
> +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
> +#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
> +
> +/*
> + * TSEC
> + */
> +#define CONFIG_TSEC_ENET /* TSEC ethernet support */
> +#define CONFIG_SYS_TSEC1_OFFSET 0x24000
> +#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
> +#define CONFIG_SYS_TSEC2_OFFSET 0x25000
> +#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
> +
> +/*
> + * TSEC ethernet configuration
> + */
> +#define CONFIG_MII 1 /* MII PHY management */
> +
> +#define CONFIG_TSEC1
> +#define CONFIG_TSEC1_NAME "eTSEC0"
> +#define TSEC1_PHY_ADDR 1
> +#define TSEC1_PHYIDX 0
> +#define TSEC1_FLAGS TSEC_GIGABIT
> +
> +#define CONFIG_TSEC2
> +#define CONFIG_TSEC2_NAME "eTSEC1"
> +#define TSEC2_PHY_ADDR 0
> +#define TSEC2_PHYIDX 0
> +#define TSEC2_FLAGS TSEC_GIGABIT
> +
> +/* Options are: eTSEC[0-1] */
> +#define CONFIG_ETHPRIME "eTSEC0"
In general we should try to have CONFIGs which enable features, and
use the device tree for config values used by drivers.
> +
> +/*
> + * Environment
> + */
> +#if 1
> +#define CONFIG_ENV_IS_IN_FLASH 1
> +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
> + CONFIG_SYS_MONITOR_LEN)
> +#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
> +#define CONFIG_ENV_SIZE 0x2000
> +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
> +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
> +#else
> +#define CONFIG_ENV_IS_NOWHERE
> +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
> +#endif
> +
> +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
> +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
> +
> +/*
> + * Command line configuration.
> + */
> +#define CONFIG_CMD_PCI
> +
> +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Drop '1' on the end of these.
> +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
> +
> +/*
> + * Miscellaneous configurable options
> + */
> +#define CONFIG_SYS_LONGHELP /* undef to save memory */
> +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
> +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
> +
> +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
> +
> +/* Print Buffer Size */
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> +
> +/*
> + * For booting Linux, the board info and command line data
> + * have to be in the first 256 MB of memory, since this is
> + * the maximum mapped by the Linux kernel during initialization.
> + */
> +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
> +
> +/*
> + * Core HID Setup
> + */
> +#define CONFIG_SYS_HID0_INIT 0x000000000
> +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
> + HID0_ENABLE_INSTRUCTION_CACHE | \
> + HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
> +#define CONFIG_SYS_HID2 HID2_HBE
> +
> +/*
> + * MMU Setup
> + */
> +
> +/* DDR: cache cacheable */
> +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
> + BATL_MEMCOHERENCE)
> +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
> + BATU_VS | BATU_VP)
> +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
> +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
> +
> +/* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
> +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
> + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
> +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
> + BATU_VP)
> +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
> +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
> +
> +/* FLASH: icache cacheable, but dcache-inhibit and guarded */
> +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
> + BATL_CACHEINHIBIT | \
> + BATL_GUARDEDSTORAGE)
> +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
> + BATU_VS | BATU_VP)
> +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
> + BATL_CACHEINHIBIT | \
> + BATL_GUARDEDSTORAGE)
> +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
> +
> +/* Stack in dcache: cacheable, no memory coherence */
> +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
> +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
> + BATU_VS | BATU_VP)
> +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
> +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
> +
> +/*
> + * Environment Configuration
> + */
> +
> +#define CONFIG_ENV_OVERWRITE
> +
> +#if defined(CONFIG_TSEC_ENET)
> +#define CONFIG_HAS_ETH0
> +#endif
> +
> +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
> +
> +#define CONFIG_HOSTNAME hrcon
> +#define CONFIG_ROOTPATH "/opt/nfsroot"
> +#define CONFIG_BOOTFILE "uImage"
> +
> +#define CONFIG_PREBOOT /* enable preboot variable */
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "netdev=eth0\0" \
> + "consoledev=ttyS1\0" \
> + "u-boot=u-boot.bin\0" \
> + "kernel_addr=1000000\0" \
> + "fdt_addr=C00000\0" \
> + "fdtfile=hrcon.dtb\0" \
> + "load=tftp ${loadaddr} ${u-boot}\0" \
> + "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
> + " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
> + " +${filesize};cp.b ${fileaddr} " \
> + __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
> + "upd=run load update\0" \
> +
> +#define CONFIG_NFSBOOTCOMMAND \
> + "setenv bootargs root=/dev/nfs rw " \
> + "nfsroot=$serverip:$rootpath " \
> + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
> + "console=$consoledev,$baudrate $othbootargs;" \
> + "tftp ${kernel_addr} $bootfile;" \
> + "tftp ${fdt_addr} $fdtfile;" \
> + "bootm ${kernel_addr} - ${fdt_addr}"
> +
> +#define CONFIG_MMCBOOTCOMMAND \
> + "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
> + "console=$consoledev,$baudrate $othbootargs;" \
> + "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
> + "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
> + "bootm ${kernel_addr} - ${fdt_addr}"
> +
> +#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
> +
> +#endif /* __CONFIG_H */
> diff --git a/include/fdt_fixup.h b/include/fdt_fixup.h
> index 9390f0a633..f67685a789 100644
> --- a/include/fdt_fixup.h
> +++ b/include/fdt_fixup.h
Hoping to drop this file.
> @@ -1,4 +1,9 @@
> struct of_board_fixup_data {
> +#ifdef CONFIG_TARGET_GAZERBEAM
> + bool var_con;
> + bool mc4;
> + bool mc2;
> +#endif
> #ifdef CONFIG_TARGET_CONTROLCENTERDC
> bool chip_exists[6];
> #endif
> --
> 2.11.0
>
Regards,
Simon
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