[U-Boot] [PATCH v3 02/10] mips: spl and normal u-boot stage set SYS_MALLOC_F_LEN indepently

Andy Yan andy.yan at rock-chips.com
Mon Jul 24 09:45:27 UTC 2017


Some platforms has very small sram to run spl code, so
it may have no enough sapce for so much malloc pool before
relocation in spl stage as the normal u-boot stage.
Use CONFIG_VAL(SYS_MALLOC_F_LEN) to fit this condition.

Signed-off-by: Andy Yan <andy.yan at rock-chips.com>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck at gmail.com>

---

Changes in v3:
- use CONFIG_VAL(), which suggested by Simon

Changes in v2: None

 arch/mips/cpu/start.S | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index d01ee9f..aa07654 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -60,8 +60,8 @@
 		sp, sp, GD_SIZE		# reserve space for gd
 	and	sp, sp, t0		# force 16 byte alignment
 	move	k0, sp			# save gd pointer
-#ifdef CONFIG_SYS_MALLOC_F_LEN
-	li	t2, CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+	li	t2, CONFIG_VAL(SYS_MALLOC_F_LEN)
 	PTR_SUBU \
 		sp, sp, t2		# reserve space for early malloc
 	and	sp, sp, t0		# force 16 byte alignment
@@ -75,7 +75,7 @@
 	blt	t0, t1, 1b
 	 PTR_ADDIU t0, PTRSIZE
 
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
 	PTR_S	sp, GD_MALLOC_BASE(k0)	# gd->malloc_base offset
 #endif
 	.endm
-- 
2.7.4




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