[U-Boot] [PATCH v2 2/4] rockchip: rk322x: update max-frequency for mmc node

[Kever Yang]

mmc using 150000000 as max-frequency like what rk3288 sets.
This can speed up the mmc read/write, the actual mmc clock is:
Before this patch: 37.125M
After this patch: 49.5M

Signed-off-by: Kever Yang <kever.yang at rock-chips.com>
---

Changes in v2:
- remove fifo-mode in patch
- update commit message to explain why this patch needed.

 arch/arm/dts/rk3229-evb.dts | 1 -
 arch/arm/dts/rk322x.dtsi    | 4 ++--
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts
index 5042c39..ae0b0a4 100644
--- a/arch/arm/dts/rk3229-evb.dts
+++ b/arch/arm/dts/rk3229-evb.dts
@@ -78,7 +78,6 @@
 	cap-sd-highspeed;
 	card-detect-delay = <200>;
 	disable-wp;
-	max-frequency = <50000000>;
 	num-slots = <1>;
 	supports-sd;
 };
diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi
index ddbe113..22324f9 100644
--- a/arch/arm/dts/rk322x.dtsi
+++ b/arch/arm/dts/rk322x.dtsi
@@ -388,6 +388,7 @@
 	sdmmc: dwmmc at 30000000 {
 		compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
 		reg = <0x30000000 0x4000>;
+		max-frequency = <150000000>;
 		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
@@ -414,9 +415,8 @@
 	emmc: dwmmc at 30020000 {
 		compatible = "rockchip,rk3288-dw-mshc";
 		reg = <0x30020000 0x4000>;
+		max-frequency = <150000000>;
 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <37500000>;
-		max-frequency = <37500000>;
 		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 		clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
-- 
1.9.1