[U-Boot] [PATCH v2 39/56] rockchip: clk: rk3368: implement MMC/SD clock reparenting

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich at theobroma-systems.com> wrote:
> The original clock support for MMC/SD cards on the RK3368 suffered
> from a tendency to select a divider less-or-equal to the the one
> giving the requested clock-rate: this can lead to higher-than-expected
> (or rather: higher than supported) clock rates for the MMC/SD
> communiction.
>
> This change rewrites the MMC/SD clock generation to:
>  * always generate a clock less-than-or-equal to the requested clock
>  * support reparenting among the CPLL, GPLL and OSC24M parents to
>    generate the highest clock that does not exceed the requested rate
>
> In addition to this, the Linux DTS uses HCLK_MMC/HCLK_SDMMC instead of
> SCLK_MMC/SCLK_SDMMC: to match this (and to ensure that clock setup
> always works), we adjust the driver appropriately.
>
> This includes the changes from:
>  - rockchip: clk: rk3368: convert MMC_PLL_SEL_* definitions to shifted-value form
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich at theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  arch/arm/include/asm/arch-rockchip/cru_rk3368.h |   8 +-
>  drivers/clk/rockchip/clk_rk3368.c               | 119 ++++++++++++++++++------
>  2 files changed, 95 insertions(+), 32 deletions(-)

Reviewed-by: Simon Glass <sjg at chromium.org>