[U-Boot] [PATCH v4 17/30] ARM: k2g: Program DDR PHY MR2 register with the default value

[Franklin S Cooper Jr]

K2G GP doesn't require the MR2 register to be programed since the
default is good enough. However, newer K2G boards do need to change
this register value. Therefore, instead of not writing this register if
ran on a K2G board just program the value to be written to match the
default/reset value.

Signed-off-by: Franklin S Cooper Jr <fcooper at ti.com>
Reviewed-by: Tom Rini <trini at konsulko.com>
---
 arch/arm/mach-keystone/ddr3.c | 3 +--
 board/ti/ks2_evm/ddr3_k2g.c   | 2 +-
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c
index ee8e12e..25a9637 100644
--- a/arch/arm/mach-keystone/ddr3.c
+++ b/arch/arm/mach-keystone/ddr3.c
@@ -52,8 +52,7 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
 	__raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
 	__raw_writel(phy_cfg->mr0,   base + KS2_DDRPHY_MR0_OFFSET);
 	__raw_writel(phy_cfg->mr1,   base + KS2_DDRPHY_MR1_OFFSET);
-	if (!cpu_is_k2g())
-		__raw_writel(phy_cfg->mr2,   base + KS2_DDRPHY_MR2_OFFSET);
+	__raw_writel(phy_cfg->mr2,   base + KS2_DDRPHY_MR2_OFFSET);
 	__raw_writel(phy_cfg->dtcr,  base + KS2_DDRPHY_DTCR_OFFSET);
 	__raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
 
diff --git a/board/ti/ks2_evm/ddr3_k2g.c b/board/ti/ks2_evm/ddr3_k2g.c
index 344961d..aeb7da6 100644
--- a/board/ti/ks2_evm/ddr3_k2g.c
+++ b/board/ti/ks2_evm/ddr3_k2g.c
@@ -27,7 +27,7 @@ struct ddr3_phy_config ddr3phy_800_2g = {
 	.dtpr2          = 0x50022A00ul,
 	.mr0            = 0x00001430ul,
 	.mr1            = 0x00000006ul,
-	.mr2            = 0x00000018ul,
+	.mr2            = 0x00000000ul,
 	.dtcr           = 0x710035C7ul,
 	.pgcr2          = 0x00F03D09ul,
 	.zq0cr1         = 0x0001005Dul,
-- 
2.10.0