[U-Boot] [PATCH v3 08/11] armv8: layerscape: Fix the sequence of changing MMU table

[york sun]

On 03/01/2017 11:32 AM, York Sun wrote:
> This patch follows the break-before-make process when making changes
> to MMU table. MMU is disabled before changing TTBR to avoid any
> potential race condition.
>
> Signed-off-by: York Sun <york.sun at nxp.com>
>
> ---
>
> Changes in v3:
>   Instead of flushing d-cache, following the break-before-make process
>   to change MMU table.
>
> Changes in v2: None
>
>  arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 18 ++++++------------
>  1 file changed, 6 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> index 800ad62..3113543 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> @@ -181,22 +181,16 @@ static inline void final_mmu_setup(void)
>  	setup_pgtables();
>  	gd->arch.tlb_addr = tlb_addr_save;
>
> -	/* flush new MMU table */
> -	flush_dcache_range(gd->arch.tlb_addr,
> -			   gd->arch.tlb_addr + gd->arch.tlb_size);
> +	/* Disable cache and MMU */
> +	dcache_disable();	/* TLBs are invalidated */
> +	invalidate_icache_all();
>
>  	/* point TTBR to the new table */
>  	set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
>  			  MEMORY_ATTRIBUTES);
> -	/*
> -	 * EL3 MMU is already enabled, just need to invalidate TLB to load the
> -	 * new table. The new table is compatible with the current table, if
> -	 * MMU somehow walks through the new table before invalidation TLB,
> -	 * it still works. So we don't need to turn off MMU here.
> -	 * When EL2 MMU table is created by calling this function, MMU needs
> -	 * to be enabled.
> -	 */
> -	set_sctlr(get_sctlr() | CR_M);
> +
> +	/* Enable MMU and D-cache */
> +	set_sctlr(get_sctlr() | CR_M | CR_C);

I made a mistake by enabling the C bit here. Will send a new version.

York