[U-Boot] [PATCH 2/3] arm: mvebu: theadorable: Add board-specific PEX detection pulse width

[Stefan Roese]

Define a board-specific detection pulse-width array for the SerDes PCIe
interfaces. If not defined in the board code, the default of currently 2
is used. Values from 0...3 are possible (2 bits).

In this case of the theadorable board, PEX interface 0 needs a value
of 0 for the detection pulse width so that the PCIe device (Atheros
WLAN PCIe device) is consistantly detected.

Signed-off-by: Stefan Roese <sr at denx.de>
Cc: Adam Shobash <adams at marvell.com>
Cc: Nadav Haklai <nadavh at marvell.com>
Cc: Konstantin Porotchkin <kostap at marvell.com>
---
 board/theadorable/theadorable.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c
index 4be7b61cd2..ab282536ec 100644
--- a/board/theadorable/theadorable.c
+++ b/board/theadorable/theadorable.c
@@ -115,6 +115,13 @@ MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = {
 	},
 };
 
+/*
+ * Define a board-specific detection pulse-width array for the SerDes PCIe
+ * interfaces. If not defined in the board code, the default of currently 2
+ * is used. Values from 0...3 are possible (2 bits).
+ */
+u8 serdes_pex_pulse_width[4] = { 0, 2, 2, 2 };
+
 MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
 {
 	/* Only one mode supported for this board */
-- 
2.12.0