[U-Boot] [PATCH v2 1/2] rockchip: rk3399: spl: add UART0 support for SPL

[Kever Yang]

Hi Philipp,

On 03/24/2017 06:24 AM, Philipp Tomsich wrote:
> The RK3399-Q7 ("Puma") SoM exposes UART0 as the Qseven UART (i.e. the
> serial line available via standardised pins on the edge connector and
> available on a RS232 connector).
>
> To support boards (such as the RK3399-Q7) that require UART0 as a
> debug console, we match CONFIG_DEBUG_UART_BASE and add the appropriate
> iomux setup to the rk3399 SPL code.
>
> As we are already touching this code, we also move the board-specific
> UART setup (i.e. iomux setup) into board_debug_uart_init(). This will
> be called from the debug UART init when CONFIG_DEBUG_UART_BOARD_INIT
> is set.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich at theobroma-systems.com>
> ---
>
> Changes in v2:
> - Changed hex constant to lowercase
>
>   arch/arm/include/asm/arch-rockchip/grf_rk3399.h |  8 +++++++
>   arch/arm/mach-rockchip/rk3399-board-spl.c       | 29 ++++++++++++++++++-------
>   2 files changed, 29 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
> index 62d8496..4701cfb 100644
> --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
> +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
> @@ -333,6 +333,14 @@ enum {
>   	GRF_GPIO2B4_SEL_MASK	= 3 << GRF_GPIO2B4_SEL_SHIFT,
>   	GRF_SPI2TPM_CSN0	= 1,
>   
> +	/* GRF_GPIO2C_IOMUX */
> +	GRF_GPIO2C0_SEL_SHIFT   = 0,
> +	GRF_GPIO2C0_SEL_MASK    = 3 << GRF_GPIO2C0_SEL_SHIFT,
> +	GRF_UART0BT_SIN         = 1,
> +	GRF_GPIO2C1_SEL_SHIFT   = 2,
> +	GRF_GPIO2C1_SEL_MASK    = 3 << GRF_GPIO2C1_SEL_SHIFT,
> +	GRF_UART0BT_SOUT        = 1,
> +
>   	/* GRF_GPIO3A_IOMUX */
>   	GRF_GPIO3A4_SEL_SHIFT	= 8,
>   	GRF_GPIO3A4_SEL_MASK	= 3 << GRF_GPIO3A4_SEL_SHIFT,
> diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c
> index 7b4e0a1..c212143 100644
> --- a/arch/arm/mach-rockchip/rk3399-board-spl.c
> +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c
> @@ -57,19 +57,22 @@ void secure_timer_init(void)
>   	writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
>   }
>   
> -#define GRF_EMMCCORE_CON11 0xff77f02c
> -void board_init_f(ulong dummy)
> +void board_debug_uart_init(void)
>   {
> -	struct udevice *pinctrl;
> -	struct udevice *dev;
> -	int ret;
> -
> -	/* Example code showing how to enable the debug UART on RK3288 */
>   #include <asm/arch/grf_rk3399.h>
> -	/* Enable early UART2 channel C on the RK3399 */
>   #define GRF_BASE	0xff770000
>   	struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
>   
> +#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
> +	/* Enable early UART0 on the RK3399 */
> +	rk_clrsetreg(&grf->gpio2c_iomux,
> +		     GRF_GPIO2C0_SEL_MASK,
> +		     GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
> +	rk_clrsetreg(&grf->gpio2c_iomux,
> +		     GRF_GPIO2C1_SEL_MASK,
> +		     GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
> +#else
> +	/* Enable early UART2 channel C on the RK3399 */
>   	rk_clrsetreg(&grf->gpio4c_iomux,
>   		     GRF_GPIO4C3_SEL_MASK,
>   		     GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
> @@ -80,6 +83,16 @@ void board_init_f(ulong dummy)
>   	rk_clrsetreg(&grf->soc_con7,
>   		     GRF_UART_DBG_SEL_MASK,
>   		     GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
> +#endif
> +}
> +
> +#define GRF_EMMCCORE_CON11 0xff77f02c
> +void board_init_f(ulong dummy)
> +{
> +	struct udevice *pinctrl;
> +	struct udevice *dev;
> +	int ret;
> +
>   #define EARLY_UART
>   #ifdef EARLY_UART
>   	/*

Reviewed-by: Kever Yang <kever.yang at rock-chips.com>

Thanks,
- Kever