[U-Boot] [PATCH] imx: i.mx6q: add the initial support for LogicPD i.MX6Q SOM
Stefano Babic
sbabic at denx.de
Fri Mar 24 11:09:20 UTC 2017
Hi Adam,
On 22/03/2017 23:07, Adam Ford wrote:
> Logic PD has an i.MX6Q system on module (SOM) with a development kit.
> This have been verified to boot the i.MX6Q version over either SD
> on the development kit or NAND built into the SOM.
A short list of supported peripherals (Ethernet,..) will help. See
commits of other i.MX6 boards.
>
> Signed-off-by: Adam Ford <aford173 at gmail.com>
>
> diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
> index 190e5c6..059d905 100644
> --- a/arch/arm/cpu/armv7/mx6/Kconfig
> +++ b/arch/arm/cpu/armv7/mx6/Kconfig
> @@ -367,6 +367,13 @@ config TARGET_ZC5601
> select DM
> select DM_THERMAL
>
> +config TARGET_MX6LOGICPD
> + bool "mx6logicpd"
> + select BOARD_LATE_INIT
> + select DM
> + select DM_THERMAL
> + select BOARD_EARLY_INIT_F
> +
> endchoice
>
> config SYS_SOC
> @@ -415,5 +422,6 @@ source "board/udoo/Kconfig"
> source "board/udoo/neo/Kconfig"
> source "board/wandboard/Kconfig"
> source "board/warp/Kconfig"
> +source "board/logicpd/imx6/Kconfig"
>
> endif
> diff --git a/board/logicpd/imx6/Kconfig b/board/logicpd/imx6/Kconfig
> new file mode 100644
> index 0000000..f5e2f58
> --- /dev/null
> +++ b/board/logicpd/imx6/Kconfig
> @@ -0,0 +1,12 @@
> +if TARGET_MX6LOGICPD
> +
> +config SYS_BOARD
> + default "imx6"
> +
> +config SYS_VENDOR
> + default "logicpd"
> +
> +config SYS_CONFIG_NAME
> + default "imx6_logic"
> +
> +endif
> diff --git a/board/logicpd/imx6/MAINTAINERS b/board/logicpd/imx6/MAINTAINERS
> new file mode 100644
> index 0000000..5db7d2c
> --- /dev/null
> +++ b/board/logicpd/imx6/MAINTAINERS
> @@ -0,0 +1,6 @@
> +MX6LOGICPD BOARD
> +M: Adam Ford <aford173 at gmail.com>
> +S: Maintained
> +F: board/logicpd/imx6/
> +F: include/configs/imx6_logic.h
> +F: configs/imx6q_logic_defconfig
> diff --git a/board/logicpd/imx6/Makefile b/board/logicpd/imx6/Makefile
> new file mode 100644
> index 0000000..397bc5e
> --- /dev/null
> +++ b/board/logicpd/imx6/Makefile
> @@ -0,0 +1,11 @@
> +#
> +# Copyright (C) 2007, Guennadi Liakhovetski <lg at denx.de>
> +#
> +# (C) Copyright 2011 Freescale Semiconductor, Inc.
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y := imx6logic.o
> +obj-$(CONFIG_POWER_PFUZE100) += ../../freescale/common/pfuze.o
> +
> diff --git a/board/logicpd/imx6/README b/board/logicpd/imx6/README
> new file mode 100644
> index 0000000..5814b9d
> --- /dev/null
> +++ b/board/logicpd/imx6/README
> @@ -0,0 +1,103 @@
> +How to use and build U-Boot on mx6sabresd:
> +----------------------------------
> +
> +Currently there are three methods for booting mx6sabresd boards:
> +
We already know how to boot sabresd - what about your board ?
I do not see support for SPL.
You should also add explanation how to install U-Boot into the NAND.
> +1. Booting via Normal U-Boot (u-boot.imx)
> +
> +2. Booting via SPL (SPL and u-boot.img)
> +
> +3. Booting via Falcon mode (SPL launches the kernel directly)
> +
> +
> +1. Booting via Normal U-Boot
> +----------------------------
> +
> +$ make mx6qsabresd_defconfig (If you want to build for mx6qsabresd)
> +
> +or
> +
> +$ make mx6dlsabresd_defconfig (If you want to build for mx6dlsabresd)
> +
> +$ make
> +
> +This will generate the image called u-boot.imx.
> +
> +- Flash the u-boot.imx binary into the SD card:
> +
> +$ sudo dd if=u-boot.imx of=/dev/sdb bs=1K seek=1 && sync
> +
> +
> +2. Booting via SPL
> +------------------
> +
> +Other method for building U-Boot on mx6qsabresd and mx6qpsabresd is
> +through SPL. In order to do so:
> +
> +$ make mx6sabresd_spl_defconfig
> +$ make
> +
> +This will generate the SPL image called SPL and the u-boot.img.
> +
> +- Flash the SPL image into the SD card:
> +
> +$ sudo dd if=SPL of=/dev/sdb bs=1K seek=1 && sync
> +
> +- Flash the u-boot.img image into the SD card:
> +
> +$ sudo dd if=u-boot.img of=/dev/sdbbs=1K seek=69 && sync
> +
> +
> +3. Booting via Falcon mode
> +--------------------------
> +
> +$ make mx6sabresd_spl_defconfig
> +$ make
> +
> +This will generate the SPL image called SPL and the u-boot.img.
> +
> +- Flash the SPL image into the SD card:
> +
> +$ sudo dd if=SPL of=/dev/sdb bs=1K seek=1 oflag=sync status=none && sync
> +
> +- Flash the u-boot.img image into the SD card:
> +
> +$ sudo dd if=u-boot.img of=/dev/sdbbs=1K seek=69 oflag=sync status=none && sync
> +
> +Create a partition for root file system and extract it there:
> +
> +$ sudo tar xvf rootfs.tar.gz -C /media/root
> +
> +The SD card must have enough space for raw "args" and "kernel".
> +To configure Falcon mode for the first time, on U-Boot do the following commands:
> +
> +- Setup the IP server:
> +
> +# setenv serverip <server_ip_address>
> +
> +- Download dtb file:
> +
> +# dhcp ${fdt_addr} imx6q-sabresd.dtb
> +
> +- Download kernel image:
> +
> +# dhcp ${loadaddr} uImage
> +
> +- Write kernel at 2MB offset:
> +
> +# mmc write ${loadaddr} 0x1000 0x4000
> +
> +- Setup kernel bootargs:
> +
> +# setenv bootargs "console=ttymxc0,115200 root=/dev/mmcblk1p1 rootfstype=ext4 rootwait quiet rw"
> +
> +- Prepare args:
> +
> +# spl export fdt ${loadaddr} - ${fdt_addr}
> +
> +- Write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)
> +
> +# mmc write 18000000 0x800 0x800
> +
> +- Press KEY_VOL_UP key, power up the board and then SPL binary will
> +launch the kernel directly.
> diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c
> new file mode 100644
> index 0000000..18ec9a1
> --- /dev/null
> +++ b/board/logicpd/imx6/imx6logic.c
> @@ -0,0 +1,364 @@
> +/*
> + * Copyright (C) 2017 Logic PD, Inc.
> + *
> + * Author: Adam Ford <aford173 at gmail.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <asm/arch/clock.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/arch/mx6-pins.h>
> +#include <linux/errno.h>
> +#include <asm/gpio.h>
> +#include <asm/imx-common/mxc_i2c.h>
> +#include <asm/imx-common/iomux-v3.h>
> +#include <asm/imx-common/boot_mode.h>
> +#include <mmc.h>
> +#include <fsl_esdhc.h>
> +#include <miiphy.h>
> +#include <netdev.h>
> +#include <asm/arch/crm_regs.h>
> +#include <asm/io.h>
> +#include <asm/arch/sys_proto.h>
> +#include <i2c.h>
> +#include <power/pmic.h>
> +#include <power/pfuze100_pmic.h>
> +#include "../../freescale/common/pfuze.h"
> +#include <asm/arch/mx6-ddr.h>
> +#include <usb.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
> + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
> + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
> +
> +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
> + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
> + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
> +
> +#define NAND_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
> + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
> + PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
> +
> +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
> + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
> +
> +#define I2C_PAD_CTRL ( \
> + PAD_CTL_SPEED_LOW | \
> + PAD_CTL_DSE_60ohm | PAD_CTL_HYS | \
> + PAD_CTL_ODE | PAD_CTL_SRE_SLOW)
> +
> +#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
> + PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
> +
> +#define I2C_PMIC 2
> +#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
> +
> +int dram_init(void)
> +{
> + gd->ram_size = imx_ddr_size();
> + return 0;
> +}
> +
> +iomux_v3_cfg_t const uart1_pads[] = {
> + MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> + MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +iomux_v3_cfg_t const uart2_pads[] = {
> + MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> + MX6_PAD_SD4_DAT5__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
> + MX6_PAD_SD4_DAT6__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
> + MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +iomux_v3_cfg_t const uart3_pads[] = {
> + MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
> + MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> + MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> + MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +iomux_v3_cfg_t const enet_pads[] = {
> + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + /* LAN8710A PHY Reset */
> + MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
> + /* LAN8710A nINT Signal */
> + MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
You have set the complete interface. It is not an issue, but pINT is
never used in U-Boot.
> +};
> +
> +static void setup_iomux_enet(void)
> +{
> + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
> +
> + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
> +
> + /* Set GPIO_16 as ENET_REF_CLK_OUT */
> + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
> +
> + /* Ensure nINT is input */
> + gpio_direction_input(IMX_GPIO_NR(4, 7));
> +
> + /* Reset LAN8710A PHY */
> + gpio_direction_output(IMX_GPIO_NR(4, 9) , 0);
> + udelay(150);
> + gpio_set_value(IMX_GPIO_NR(4, 9), 1);
> + mdelay(50);
> +}
> +
> +iomux_v3_cfg_t const usdhc1_pads[] = {
> + MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +iomux_v3_cfg_t const usdhc2_pads[] = {
> + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +
> +static struct i2c_pads_info i2c_pad_info3 = {
> + .scl = {
> + .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
> + .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(I2C_PAD_CTRL),
> + .gp = IMX_GPIO_NR(3, 17)
> + },
> + .sda = {
> + .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
> + .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | MUX_PAD_CTRL(I2C_PAD_CTRL),
> + .gp = IMX_GPIO_NR(3, 18)
> + }
> +};
> +
> +static void setup_iomux_uart(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
> + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
> + imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
> +}
> +
> +iomux_v3_cfg_t const pmic_pads[] = {
> + MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static void setup_pmic_pins(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(pmic_pads, ARRAY_SIZE(pmic_pads));
> +}
> +
> +iomux_v3_cfg_t const nand_pads[] = {
> + MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
> +};
> +
> +static void setup_nand_pins(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
> +}
> +
> +#ifdef CONFIG_FSL_ESDHC
> +struct fsl_esdhc_cfg usdhc_cfg[] = {
> + {USDHC1_BASE_ADDR},
> + {USDHC2_BASE_ADDR},
> +};
> +
> +#define USDHC1_CD_GPIO IMX_GPIO_NR(6, 16)
> +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
> +
> +int board_mmc_get_env_dev(int devno)
> +{
> + return devno - 1;
> +}
> +
> +int board_mmc_getcd(struct mmc *mmc)
> +{
> + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
> + int ret = 0;
> +
> + switch (cfg->esdhc_base) {
> + case USDHC1_BASE_ADDR:
> + ret = !gpio_get_value(USDHC1_CD_GPIO);
> + break;
> + case USDHC2_BASE_ADDR:
> + ret = !gpio_get_value(USDHC2_CD_GPIO);
> + break;
> + }
> +
> + return ret;
> +}
> +
> +int board_mmc_init(bd_t *bis)
> +{
> + int ret;
> + int i;
> +
> + /*
> + * According to the board_mmc_init() the following map is done:
> + * (U-Boot device node) (Physical Port)
> + * mmc0 SOM
> + * mmc1 Baseboard
> + * mmc2 eMMC
> + */
> + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
> + switch (i) {
> + case 0:
> + imx_iomux_v3_setup_multiple_pads(
> + usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
> + gpio_direction_input(USDHC1_CD_GPIO);
> + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
> + break;
> + case 1:
> + imx_iomux_v3_setup_multiple_pads(
> + usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
> + gpio_direction_input(USDHC2_CD_GPIO);
> + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
> + break;
> + default:
> + printf("Warning: you configured more USDHC controllers");
> + printf("(%d) then supported by the board (%d)\n",
> + i + 1, CONFIG_SYS_FSL_USDHC_NUM);
> + return -EINVAL;
> + }
> +
> + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
> + if (ret)
> + return ret;
> + }
> + return 0;
> +}
> +#endif
> +
> +int board_phy_config(struct phy_device *phydev)
> +{
> + if (phydev->drv->config)
> + phydev->drv->config(phydev);
> +
> + return 0;
> +}
> +
> +/*
> + * Do not overwrite the console
> + * Use always serial for U-Boot console
> + */
> +int overwrite_console(void)
> +{
> + return 1;
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> + setup_iomux_enet();
> + return cpu_eth_init(bis);
> +}
> +
> +int board_early_init_f(void)
> +{
> + setup_iomux_uart();
> + setup_pmic_pins();
> + setup_nand_pins();
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> + /* address of boot parameters */
> + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
> +#ifdef CONFIG_FEC_MXC
I think we should start to get rid of these annoying #ifdef. The board
has always FEC, right ?
> + enable_fec_anatop_clock(0, ENET_50MHZ);
> +#endif
> +
> + setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, &i2c_pad_info3);
> +
> + return 0;
> +}
> +
> +int power_init_board(void)
> +{
> + struct pmic *p;
> +
> + p = pfuze_common_init(I2C_PMIC);
> + if (!p)
> + return -ENODEV;
> +
> + return pfuze_mode_init(p, APS_PFM);
> +}
> +
> +#ifdef CONFIG_CMD_BMODE
> +static const struct boot_mode board_boot_modes[] = {
> + /* 4 bit bus width */
> + /* 4 bit bus width */
> + {"sd1", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
> + {"sd2", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
> + {NULL, 0},
> +};
> +#endif
> +
> +int board_late_init(void)
> +{
> +#ifdef CONFIG_CMD_BMODE
> + add_board_boot_modes(board_boot_modes);
> +#endif
> +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> + setenv("board_name", "imx6_logicpd");
> +
> + if (is_mx6dqp()) {
> + setenv("board_rev", "MX6QP");
> + setenv("fdt_file", "imx6q-logicpd.dtb");
Do you need the same thing as sabre ? If we check the name, more as
"board_rev" this is a "soc_type". I know that the same is in sabre, I
just ask if this is correct. It is like a misuse.
> + }
> + else if (is_mx6dq()) {
> + setenv("board_rev", "MX6Q");
> + setenv("fdt_file", "imx6q-logicpd.dtb");
> + }
> + else if (is_mx6sdl()) {
> + setenv("board_rev", "MX6DL");
> + setenv("fdt_file", "imx6sdl-logicpd.dtb");
> + }
> + else if (is_mx6solo()) {
> + setenv("board_rev", "MX6SOLO");
> + setenv("fdt_file", "imx6sdl-logicpd.dtb");
> + }
> +#endif
> + return 0;
> +}
> +
> +int checkboard(void)
> +{
> + puts("Board: Logic PD i.MX6 SOM\n");
> + return 0;
> +}
> diff --git a/board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg b/board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg
> new file mode 100644
> index 0000000..f22db03
> --- /dev/null
> +++ b/board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg
> @@ -0,0 +1,217 @@
> +/*
> + * Copyright (C) 2017 Logic PD, Inc.
> + * Adam Ford <aford173 at gmail.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + *
> + * Refer doc/README.imximage for more details about how-to configure
> + * and create imximage boot image
> + *
> + * The syntax is taken as close as possible with the kwbimage
> + */
> +
> +/* image version */
> +IMAGE_VERSION 2
> +
> +/*
> + * Boot Device : sd or nand
> + * nand: flash_offset: 0x0400
> + * sd/mmc: flash_offset: 0x0400
> + */
> +
> +/* the same flash_offset as sd */
> +BOOT_FROM sd
...but I have read you boot from NAND, too. Something is not consistent.
> +
> +/*
> + * Device Configuration Data (DCD)
> + *
> + * Each entry must have the format:
> + * Addr-type Address Value
> + *
> + * where:
> + * Addr-type register length (1,2 or 4 bytes)
> + * Address absolute address of the register
> + * value value to be stored in the register
> + */
> +
> +/* Settings derived from MX6DQSDL DDR3 Script Aid spreadsheet version 0.08 */
> +
> +//=============================================================================
> +//init script for i.Mx6D DDR3
// are not accepted as comment in U-Boot
> +//=============================================================================
> +// Revision History
> +// v01
> +//=============================================================================
> +
> +
> +//=============================================================================
> +// IOMUX
> +//=============================================================================
> +//DDR IO TYPE:
> +DATA 4 0x020e0798 0x000C0000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
> +DATA 4 0x020e0758 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE
> +
> +//CLOCK:
> +DATA 4 0x020e0588 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
> +DATA 4 0x020e0594 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
> +
> +//ADDRESS:
> +DATA 4 0x020e056c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
> +DATA 4 0x020e0578 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
> +DATA 4 0x020e074c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_ADDDS
> +
> +//Control:
> +DATA 4 0x020e057c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
> +DATA 4 0x020e058c 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS
> +DATA 4 0x020e059c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
> +DATA 4 0x020e05a0 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
> +DATA 4 0x020e078c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_CTLDS
> +
> +//Data Strobes:
> +DATA 4 0x020e0750 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
> +DATA 4 0x020e05a8 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
> +DATA 4 0x020e05b0 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
> +DATA 4 0x020e0524 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
> +DATA 4 0x020e051c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
> +//DATA 4 0x020e0518 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4
> +//DATA 4 0x020e050c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5
> +//DATA 4 0x020e05b8 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6
> +//DATA 4 0x020e05c0 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7
> +
> +//Data:
> +DATA 4 0x020e0774 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE
> +DATA 4 0x020e0784 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B0DS
> +DATA 4 0x020e0788 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B1DS
> +DATA 4 0x020e0794 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B2DS
> +DATA 4 0x020e079c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B3DS
> +//DATA 4 0x020e07a0 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B4DS
> +//DATA 4 0x020e07a4 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B5DS
> +//DATA 4 0x020e07a8 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B6DS
> +//DATA 4 0x020e0748 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B7DS
No dead code, please
Anyway, these are default values for DDR controller - why do you need ?
> +
> +DATA 4 0x020e05ac 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
> +DATA 4 0x020e05b4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
> +DATA 4 0x020e0528 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
> +DATA 4 0x020e0520 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
> +//DATA 4 0x020e0514 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4
> +//DATA 4 0x020e0510 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5
> +//DATA 4 0x020e05bc 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6
> +//DATA 4 0x020e05c4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7
> +
> +
> +//=============================================================================
> +// DDR Controller Registers
> +//=============================================================================
> +// Manufacturer: Micron
> +// Device Part Number: MT41K512M16HA-125
> +// Clock Freq.: 528MHz
> +// Density per CS in Gb: 16
> +// Chip Selects used: 1
> +// Number of Banks: 8
> +// Row address: 16
> +// Column address: 10
> +// Data bus width 32
> +//=============================================================================
> +DATA 4 0x021b001c 0x00008000 //MMDC0_MDSCR set the Configuration request bit during MMDC set up
> +
> +//=============================================================================
> +// Calibration setup.
> +//=============================================================================
> +DATA 4 0x021b0800 0xA1390003 // DDR_PHY_P0_MPZQHWCTRL enable both one-time & periodic HW ZQ calibration.
> +
> +// For target board may need to run write leveling calibration to fine tune these settings.
> +DATA 4 0x021b080c 0x002D003A // MMDC1_MPWLDECTRL0
> +DATA 4 0x021b0810 0x0038002B // MMDC1_MPWLDECTRL1
> +//DATA 4 0x021b480c 0x00000000
> +//DATA 4 0x021b4810 0x00000000
> +
> +////Read DQS Gating calibration
> +DATA 4 0x021b083c 0x03340338 // MPDGCTRL0 PHY0
> +DATA 4 0x021b0840 0x0334032C // MPDGCTRL1 PHY0
> +//DATA 4 0x021b483c 0x00000000 // MPDGCTRL0 PHY1
> +//DATA 4 0x021b4840 0x00000000 // MPDGCTRL1 PHY1
> +
> +//Read calibration
> +DATA 4 0x021b0848 0x4036383C // MPRDDLCTL PHY0
> +//DATA 4 0x021b4848 0x40404040 // MPRDDLCTL PHY1
> +
> +//Write calibration
> +DATA 4 0x021b0850 0x2E384038 // MPWRDLCTL PHY0
> +//DATA 4 0x021b4850 0x40404040 // MPWRDLCTL PHY1
> +
> +//read data bit delay: (3 is the reccommended default value although out of reset value is 0)
> +DATA 4 0x021b081c 0x33333333 // DDR_PHY_P0_MPREDQBY0DL3
> +DATA 4 0x021b0820 0x33333333 // DDR_PHY_P0_MPREDQBY1DL3
> +DATA 4 0x021b0824 0x33333333 // DDR_PHY_P0_MPREDQBY2DL3
> +DATA 4 0x021b0828 0x33333333 // DDR_PHY_P0_MPREDQBY3DL3
> +//DATA 4 0x021b481c 0x33333333 // DDR_PHY_P1_MPREDQBY0DL3
> +//DATA 4 0x021b4820 0x33333333 // DDR_PHY_P1_MPREDQBY1DL3
> +//DATA 4 0x021b4824 0x33333333 // DDR_PHY_P1_MPREDQBY2DL3
> +//DATA 4 0x021b4828 0x33333333 // DDR_PHY_P1_MPREDQBY3DL3
> +
> +//For i.mx6qd parts of versions A & B (v1.0 v1.1) uncomment the following lines. For version C (v1.2) keep commented
> +//DATA 4 0x021b08c0 0x24911492 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6
> +//DATA 4 0x021b48c0 0x24911492
???
If there something that depends on SOC version, it should be done in
code by checking the HW revision and not hard-coding it into DCD.
> +
> +// Complete calibration by forced measurement:
> +DATA 4 0x021b08b8 0x00000800 // DDR_PHY_P0_MPMUR0 frc_msr
> +//DATA 4 0x021b48b8 0x00000800 // DDR_PHY_P0_MPMUR0 frc_msr
> +//=============================================================================
> +// Calibration setup end
> +//=============================================================================
> +
> +//MMDC init:
> +DATA 4 0x021b0004 0x00020036 // MMDC0_MDPDC
> +DATA 4 0x021b0008 0x09444040 // MMDC0_MDOTC
> +DATA 4 0x021b000c 0xB8BE7955 // MMDC0_MDCFG0
> +DATA 4 0x021b0010 0xFF328F64 // MMDC0_MDCFG1
> +DATA 4 0x021b0014 0x01FF00DB // MMDC0_MDCFG2
> +
> +//MDMISC: RALAT kept to the high level of 5.
> +//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
> +//a. better operation at low frequency for LPDDR2 freq < 100MHz change RALAT to 3
> +//b. Small performence improvment
> +DATA 4 0x021b0018 0x00011740 // MMDC0_MDMISC
> +DATA 4 0x021b001c 0x00008000 // MMDC0_MDSCR set the Configuration request bit during MMDC set up
> +DATA 4 0x021b002c 0x000026D2 // MMDC0_MDRWD
> +DATA 4 0x021b0030 0x00BE1023 // MMDC0_MDOR
> +DATA 4 0x021b0040 0x00000047 // Chan0 CS0_END
> +DATA 4 0x021b0000 0x85190000 // MMDC0_MDCTL
> +
> +//Mode register writes
> +DATA 4 0x021b001c 0x00888032 // MMDC0_MDSCR MR2 write CS0
> +DATA 4 0x021b001c 0x00008033 // MMDC0_MDSCR MR3 write CS0
> +DATA 4 0x021b001c 0x00008031 // MMDC0_MDSCR MR1 write CS0
> +DATA 4 0x021b001c 0x19408030 // MMDC0_MDSCR MR0write CS0
> +DATA 4 0x021b001c 0x04008040 // MMDC0_MDSCR ZQ calibration command sent to device on CS0
> +
> +//DATA 4 0x021b001c 0x0088803A // MMDC0_MDSCR MR2 write CS1
> +//DATA 4 0x021b001c 0x0000803B // MMDC0_MDSCR MR3 write CS1
> +//DATA 4 0x021b001c 0x00008039 // MMDC0_MDSCR MR1 write CS1
> +//DATA 4 0x021b001c 0x19408038 // MMDC0_MDSCR MR0write CS1
> +//DATA 4 0x021b001c 0x04008048 // MMDC0_MDSCR ZQ calibration command sent to device on CS1
> +
> +DATA 4 0x021b0020 0x00007800 // MMDC0_MDREF
> +
> +DATA 4 0x021b0818 0x00000007 // DDR_PHY_P0_MPODTCTRL
> +//DATA 4 0x021b4818 0x00000007 // DDR_PHY_P1_MPODTCTRL
> +
> +DATA 4 0x021b0004 0x00025576 // MMDC0_MDPDC now SDCTL power down enabled
> +
> +DATA 4 0x021b0404 0x00011006 // MMDC0_MAPSR ADOPT power down enabled MMDC will enter automatically to self-refresh while the number of idle cycle reached.
> +
> +DATA 4 0x021b001c 0x00000000 // MMDC0_MDSCR clear this register (especially the configuration bit as initialization is complete)
> +/* set the default clock gate to save power */
> +DATA 4 0x020c4068 0x00C03F3F
> +DATA 4 0x020c406c 0x0030FC03
> +DATA 4 0x020c4070 0x0FFFC000
> +DATA 4 0x020c4074 0x3FF00000
> +DATA 4 0x020c4078 0xFFFFF300
> +DATA 4 0x020c407c 0x0F0000F3
> +DATA 4 0x020c4080 0x00000FFF
> +
I am still missing why we have to code this into the DCD instead of
using the code provided by U-Boot. There are functions to setup the DDR
controller and even (thanks to Marek !) for dynamic calibration. And
yes, there are much more easy to maintain as these chunk of hexadecimal
values.
> +/* enable AXI cache for VDOA/VPU/IPU */
> +DATA 4 0x020e0010 0xF00000CF
> +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
> +DATA 4 0x020e0018 0x007F007F
> +DATA 4 0x020e001c 0x007F007F
Same here, it is normally part of common i.MX code.
> \ No newline at end of file
> diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig
> new file mode 100644
> index 0000000..1526d38
> --- /dev/null
> +++ b/configs/imx6q_logic_defconfig
> @@ -0,0 +1,30 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_MX6=y
> +CONFIG_TARGET_MX6LOGICPD=y
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg,MX6Q"
> +CONFIG_BOOTDELAY=3
> +# CONFIG_CONSOLE_MUX is not set
> +CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
> +CONFIG_HUSH_PARSER=y
> +CONFIG_SYS_PROMPT="i.MX6 Logic # "
> +CONFIG_CMD_BOOTZ=y
> +# CONFIG_CMD_IMLS is not set
> +# CONFIG_CMD_FLASH is not set
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_NAND=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_DHCP=y
> +CONFIG_CMD_MII=y
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_EXT2=y
> +CONFIG_CMD_EXT4=y
> +CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_CMD_FAT=y
> +CONFIG_CMD_FS_GENERIC=y
> +CONFIG_NAND_MXS=y
> +CONFIG_DISPLAY_CPUINFO=y
> +CONFIG_CMD_MEMTEST=y
> +CONFIG_OF_LIBFDT=y
> diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h
> new file mode 100644
> index 0000000..556cad2
> --- /dev/null
> +++ b/include/configs/imx6_logic.h
> @@ -0,0 +1,194 @@
> +/*
> + * Copyright (C) 2017 Logic PD, Inc.
> + *
> + * Configuration settings for the LogicPD i.MX6 SOM.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __IMX6LOGIC_CONFIG_H
> +#define __IMX6LOGIC_CONFIG_H
> +
> +#define CONFIG_MACH_TYPE 3980
> +#define CONFIG_MXC_UART_BASE UART1_BASE
> +#define CONSOLE_DEV "ttymxc0"
> +
> +#include "mx6_common.h"
> +
> +#define CONFIG_IMX_THERMAL
> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
> +
> +#define CONFIG_MXC_UART
> +
> +/* MMC Configs */
> +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> +#define CONFIG_SYS_FSL_USDHC_NUM 2
> +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* Dev kit SD card */
> +
> +/* Ethernet Configs */
> +#define CONFIG_FEC_MXC
> +#define CONFIG_MII
> +#define IMX_FEC_BASE ENET_BASE_ADDR
> +#define CONFIG_FEC_XCV_TYPE RMII
> +#define CONFIG_ETHPRIME "FEC"
> +#define CONFIG_FEC_MXC_PHYADDR 0
> +#define CONFIG_PHYLIB
> +#define CONFIG_PHY_SMSC
> +
> +/* Command definition */
> +#define CONFIG_CMD_BMODE
> +
> +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "script=boot.scr\0" \
> + "image=zImage\0" \
> + "fdt_addr=0x18000000\0" \
> + "ramdisk_addr=0x13000000\0" \
> + "ramdisk_file=rootfs.cpio.uboot\0" \
> + "boot_fdt=try\0" \
> + "ip_dyn=yes\0" \
> + "console=" CONSOLE_DEV "\0" \
> + "fdt_high=0xffffffff\0" \
> + "initrd_high=0xffffffff\0" \
> + "mmcdev=1\0" \
> + "mmcpart=1\0" \
> + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
> + "nandroot=ubi0:rootfs rootfstype=ubifs\0" \
> + "mmcargs=setenv bootargs console=${console},${baudrate}" \
> + " root=${mmcroot} ${mtdparts}\0" \
> + "nandargs=setenv bootargs console=${console},${baudrate}" \
> + " ubi.mtd=fs root=${nandroot} ${mtdparts}\0" \
> + "ramargs=setenv bootargs console=${console},${baudrate}" \
> + " root=/dev/ram rw ${mtdparts}\0" \
> + "loadbootscript=" \
> + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
> + "bootscript=echo Running bootscript from mmc ...;" \
> + " source\0" \
> + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
> + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
> + "loadramdisk=fatload mmc ${mmcdev}:${mmcpart} ${ramdisk_addr} ${ramdisk_file}\0" \
> + "mmcboot=echo Booting from mmc...; run mmcargs; run loadimage;" \
> + " run loadfdt; bootz ${loadaddr} - ${fdt_addr}\0" \
> + "mmcramboot=run ramargs; run loadimage;" \
> + " run loadfdt; run loadramdisk;" \
> + " bootz ${loadaddr} ${ramdisk_addr} ${fdt_addr}\0" \
> + "nandboot=echo Booting from nand ...; " \
> + " run nandargs;" \
> + " nand read ${loadaddr} kernel;" \
> + " nand read ${fdt_addr} dtb;" \
> + " bootz ${loadaddr} - ${fdt_addr}\0" \
> + "nandramboot=echo Booting RAMdisk from nand ...; " \
> + " nand read ${ramdisk_addr} fs ${ramdisksize};" \
> + " nand read ${loadaddr} kernel;" \
> + " nand read ${fdt_addr} dtb;" \
> + " run ramargs;" \
> + " bootz ${loadaddr} ${ramdisk_addr} ${fdt_addr}\0" \
> + "netargs=setenv bootargs console=${console},${baudrate} " \
> + "root=/dev/nfs" \
> + " ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
> + "netboot=echo Booting from net ...; " \
> + "run netargs; " \
> + "if test ${ip_dyn} = yes; then " \
> + "setenv get_cmd dhcp; " \
> + "else " \
> + "setenv get_cmd tftp; " \
> + "fi; " \
> + "${get_cmd} ${image}; " \
> + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
> + "bootz ${loadaddr} - ${fdt_addr}; " \
> + "else " \
> + "if test ${boot_fdt} = try; then " \
> + "bootz; " \
> + "else " \
> + "echo WARN: Cannot load the DT; " \
> + "fi; " \
> + "fi; " \
> + "else " \
> + "bootz; " \
> + "fi;\0" \
> + "autoboot=mmc dev ${mmcdev};" \
> + "if mmc rescan; then " \
> + "if run loadbootscript; then " \
> + "run bootscript; " \
> + "else " \
> + "if run loadimage; then " \
> + "run mmcboot; " \
> + "else run netboot; " \
> + "fi; " \
> + "fi; " \
> + "else run netboot; fi"
> +#define CONFIG_BOOTCOMMAND \
> + "run autoboot"
> +
> +#define CONFIG_ARP_TIMEOUT 200UL
> +
> +#define CONFIG_SYS_MEMTEST_START 0x10000000
> +#define CONFIG_SYS_MEMTEST_END 0x10010000
> +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
> +
> +#define CONFIG_STACKSIZE (128 * 1024)
> +
> +/* Physical Memory Map */
> +#define CONFIG_NR_DRAM_BANKS 1
> +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
> +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
> +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
> +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +/* Environment organization */
> +#define CONFIG_ENV_SIZE (8 * 1024)
> +#define CONFIG_ENV_IS_IN_NAND
> +#define CONFIG_ENV_OFFSET 0x400000
> +#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
> +
> +
> +/* I2C Configs */
> +#define CONFIG_SYS_I2C
> +#define CONFIG_SYS_I2C_MXC
> +#define CONFIG_SYS_I2C_MXC_I2C1
> +#define CONFIG_SYS_I2C_MXC_I2C2
> +#define CONFIG_SYS_I2C_MXC_I2C3
> +#define CONFIG_SYS_I2C_SPEED 400000
> +#define CONFIG_SYS_I2C_SLAVE 0x8
> +
> +/* NAND flash command */
> +
> +#define CONFIG_CMD_NAND_TRIMFFS
> +
> +/* NAND stuff */
> +#define CONFIG_SYS_MAX_NAND_DEVICE 1
> +#define CONFIG_SYS_NAND_BASE 0x40000000
> +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
> +#define CONFIG_SYS_NAND_ONFI_DETECTION
> +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
> +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
> +
> +/* MTD device */
> +# define CONFIG_MTD_DEVICE
> +# define CONFIG_CMD_MTDPARTS
> +# define CONFIG_MTD_PARTITIONS
> +# define MTDIDS_DEFAULT "nand0=gpmi-nand"
> +# define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:4m(uboot)," \
> + "1m(env),8m(kernel),1m(dtb),-(fs)"
> +
> +/* DMA stuff, needed for GPMI/MXS NAND support */
> +#define CONFIG_APBH_DMA
> +#define CONFIG_APBH_DMA_BURST
> +#define CONFIG_APBH_DMA_BURST8
> +
> +/* PMIC */
> +#define CONFIG_POWER
> +#define CONFIG_POWER_I2C
> +#define CONFIG_POWER_PFUZE100
> +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
> +
> +#endif /* __IMX6LOGIC_CONFIG_H */
>
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
More information about the U-Boot
mailing list