[U-Boot] [PATCH] imx: i.mx6q: add the initial support for LogicPD i.MX6Q SOM
Adam Ford
aford173 at gmail.com
Fri Mar 24 13:28:01 UTC 2017
On Fri, Mar 24, 2017 at 6:09 AM, Stefano Babic <sbabic at denx.de> wrote:
> Hi Adam,
>
> On 22/03/2017 23:07, Adam Ford wrote:
>> Logic PD has an i.MX6Q system on module (SOM) with a development kit.
>> This have been verified to boot the i.MX6Q version over either SD
>> on the development kit or NAND built into the SOM.
>
> A short list of supported peripherals (Ethernet,..) will help. See
> commits of other i.MX6 boards.
>
>>
>> Signed-off-by: Adam Ford <aford173 at gmail.com>
>>
>> diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
>> index 190e5c6..059d905 100644
>> --- a/arch/arm/cpu/armv7/mx6/Kconfig
>> +++ b/arch/arm/cpu/armv7/mx6/Kconfig
>> @@ -367,6 +367,13 @@ config TARGET_ZC5601
>> select DM
>> select DM_THERMAL
>>
>> +config TARGET_MX6LOGICPD
>> + bool "mx6logicpd"
>> + select BOARD_LATE_INIT
>> + select DM
>> + select DM_THERMAL
>> + select BOARD_EARLY_INIT_F
>> +
>> endchoice
>>
>> config SYS_SOC
>> @@ -415,5 +422,6 @@ source "board/udoo/Kconfig"
>> source "board/udoo/neo/Kconfig"
>> source "board/wandboard/Kconfig"
>> source "board/warp/Kconfig"
>> +source "board/logicpd/imx6/Kconfig"
>>
>> endif
>> diff --git a/board/logicpd/imx6/Kconfig b/board/logicpd/imx6/Kconfig
>> new file mode 100644
>> index 0000000..f5e2f58
>> --- /dev/null
>> +++ b/board/logicpd/imx6/Kconfig
>> @@ -0,0 +1,12 @@
>> +if TARGET_MX6LOGICPD
>> +
>> +config SYS_BOARD
>> + default "imx6"
>> +
>> +config SYS_VENDOR
>> + default "logicpd"
>> +
>> +config SYS_CONFIG_NAME
>> + default "imx6_logic"
>> +
>> +endif
>> diff --git a/board/logicpd/imx6/MAINTAINERS b/board/logicpd/imx6/MAINTAINERS
>> new file mode 100644
>> index 0000000..5db7d2c
>> --- /dev/null
>> +++ b/board/logicpd/imx6/MAINTAINERS
>> @@ -0,0 +1,6 @@
>> +MX6LOGICPD BOARD
>> +M: Adam Ford <aford173 at gmail.com>
>> +S: Maintained
>> +F: board/logicpd/imx6/
>> +F: include/configs/imx6_logic.h
>> +F: configs/imx6q_logic_defconfig
>> diff --git a/board/logicpd/imx6/Makefile b/board/logicpd/imx6/Makefile
>> new file mode 100644
>> index 0000000..397bc5e
>> --- /dev/null
>> +++ b/board/logicpd/imx6/Makefile
>> @@ -0,0 +1,11 @@
>> +#
>> +# Copyright (C) 2007, Guennadi Liakhovetski <lg at denx.de>
>> +#
>> +# (C) Copyright 2011 Freescale Semiconductor, Inc.
>> +#
>> +# SPDX-License-Identifier: GPL-2.0+
>> +#
>> +
>> +obj-y := imx6logic.o
>> +obj-$(CONFIG_POWER_PFUZE100) += ../../freescale/common/pfuze.o
>> +
>> diff --git a/board/logicpd/imx6/README b/board/logicpd/imx6/README
>> new file mode 100644
>> index 0000000..5814b9d
>> --- /dev/null
>> +++ b/board/logicpd/imx6/README
>> @@ -0,0 +1,103 @@
>> +How to use and build U-Boot on mx6sabresd:
>> +----------------------------------
>> +
>> +Currently there are three methods for booting mx6sabresd boards:
>> +
>
> We already know how to boot sabresd - what about your board ?
>
> I do not see support for SPL.
>
> You should also add explanation how to install U-Boot into the NAND.
>
>> +1. Booting via Normal U-Boot (u-boot.imx)
>> +
>> +2. Booting via SPL (SPL and u-boot.img)
>> +
>> +3. Booting via Falcon mode (SPL launches the kernel directly)
>> +
>> +
>> +1. Booting via Normal U-Boot
>> +----------------------------
>> +
>> +$ make mx6qsabresd_defconfig (If you want to build for mx6qsabresd)
>> +
>> +or
>> +
>> +$ make mx6dlsabresd_defconfig (If you want to build for mx6dlsabresd)
>> +
>> +$ make
>> +
>> +This will generate the image called u-boot.imx.
>> +
>> +- Flash the u-boot.imx binary into the SD card:
>> +
>> +$ sudo dd if=u-boot.imx of=/dev/sdb bs=1K seek=1 && sync
>> +
>> +
>> +2. Booting via SPL
>> +------------------
>> +
>> +Other method for building U-Boot on mx6qsabresd and mx6qpsabresd is
>> +through SPL. In order to do so:
>> +
>> +$ make mx6sabresd_spl_defconfig
>> +$ make
>> +
>> +This will generate the SPL image called SPL and the u-boot.img.
>> +
>> +- Flash the SPL image into the SD card:
>> +
>> +$ sudo dd if=SPL of=/dev/sdb bs=1K seek=1 && sync
>> +
>> +- Flash the u-boot.img image into the SD card:
>> +
>> +$ sudo dd if=u-boot.img of=/dev/sdbbs=1K seek=69 && sync
>> +
>> +
>> +3. Booting via Falcon mode
>> +--------------------------
>> +
>> +$ make mx6sabresd_spl_defconfig
>> +$ make
>> +
>> +This will generate the SPL image called SPL and the u-boot.img.
>> +
>> +- Flash the SPL image into the SD card:
>> +
>> +$ sudo dd if=SPL of=/dev/sdb bs=1K seek=1 oflag=sync status=none && sync
>> +
>> +- Flash the u-boot.img image into the SD card:
>> +
>> +$ sudo dd if=u-boot.img of=/dev/sdbbs=1K seek=69 oflag=sync status=none && sync
>> +
>> +Create a partition for root file system and extract it there:
>> +
>> +$ sudo tar xvf rootfs.tar.gz -C /media/root
>> +
>> +The SD card must have enough space for raw "args" and "kernel".
>> +To configure Falcon mode for the first time, on U-Boot do the following commands:
>> +
>> +- Setup the IP server:
>> +
>> +# setenv serverip <server_ip_address>
>> +
>> +- Download dtb file:
>> +
>> +# dhcp ${fdt_addr} imx6q-sabresd.dtb
>> +
>> +- Download kernel image:
>> +
>> +# dhcp ${loadaddr} uImage
>> +
>> +- Write kernel at 2MB offset:
>> +
>> +# mmc write ${loadaddr} 0x1000 0x4000
>> +
>> +- Setup kernel bootargs:
>> +
>> +# setenv bootargs "console=ttymxc0,115200 root=/dev/mmcblk1p1 rootfstype=ext4 rootwait quiet rw"
>> +
>> +- Prepare args:
>> +
>> +# spl export fdt ${loadaddr} - ${fdt_addr}
>> +
>> +- Write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)
>> +
>> +# mmc write 18000000 0x800 0x800
>> +
>> +- Press KEY_VOL_UP key, power up the board and then SPL binary will
>> +launch the kernel directly.
>> diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c
>> new file mode 100644
>> index 0000000..18ec9a1
>> --- /dev/null
>> +++ b/board/logicpd/imx6/imx6logic.c
>> @@ -0,0 +1,364 @@
>> +/*
>> + * Copyright (C) 2017 Logic PD, Inc.
>> + *
>> + * Author: Adam Ford <aford173 at gmail.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <asm/arch/clock.h>
>> +#include <asm/arch/imx-regs.h>
>> +#include <asm/arch/iomux.h>
>> +#include <asm/arch/mx6-pins.h>
>> +#include <linux/errno.h>
>> +#include <asm/gpio.h>
>> +#include <asm/imx-common/mxc_i2c.h>
>> +#include <asm/imx-common/iomux-v3.h>
>> +#include <asm/imx-common/boot_mode.h>
>> +#include <mmc.h>
>> +#include <fsl_esdhc.h>
>> +#include <miiphy.h>
>> +#include <netdev.h>
>> +#include <asm/arch/crm_regs.h>
>> +#include <asm/io.h>
>> +#include <asm/arch/sys_proto.h>
>> +#include <i2c.h>
>> +#include <power/pmic.h>
>> +#include <power/pfuze100_pmic.h>
>> +#include "../../freescale/common/pfuze.h"
>> +#include <asm/arch/mx6-ddr.h>
>> +#include <usb.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
>> + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
>> + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
>> +
>> +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
>> + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
>> + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
>> +
>> +#define NAND_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
>> + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
>> + PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
>> +
>> +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
>> + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
>> +
>> +#define I2C_PAD_CTRL ( \
>> + PAD_CTL_SPEED_LOW | \
>> + PAD_CTL_DSE_60ohm | PAD_CTL_HYS | \
>> + PAD_CTL_ODE | PAD_CTL_SRE_SLOW)
>> +
>> +#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
>> + PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
>> +
>> +#define I2C_PMIC 2
>> +#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
>> +
>> +int dram_init(void)
>> +{
>> + gd->ram_size = imx_ddr_size();
>> + return 0;
>> +}
>> +
>> +iomux_v3_cfg_t const uart1_pads[] = {
>> + MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
>> + MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
>> +};
>> +
>> +iomux_v3_cfg_t const uart2_pads[] = {
>> + MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
>> + MX6_PAD_SD4_DAT5__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
>> + MX6_PAD_SD4_DAT6__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
>> + MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
>> +};
>> +
>> +iomux_v3_cfg_t const uart3_pads[] = {
>> + MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
>> + MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
>> + MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
>> + MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
>> +};
>> +
>> +iomux_v3_cfg_t const enet_pads[] = {
>> + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + /* LAN8710A PHY Reset */
>> + MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
>> + /* LAN8710A nINT Signal */
>> + MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
>
> You have set the complete interface. It is not an issue, but pINT is
> never used in U-Boot.
>
>> +};
>> +
>> +static void setup_iomux_enet(void)
>> +{
>> + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
>> +
>> + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
>> +
>> + /* Set GPIO_16 as ENET_REF_CLK_OUT */
>> + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
>> +
>> + /* Ensure nINT is input */
>> + gpio_direction_input(IMX_GPIO_NR(4, 7));
>> +
>> + /* Reset LAN8710A PHY */
>> + gpio_direction_output(IMX_GPIO_NR(4, 9) , 0);
>> + udelay(150);
>> + gpio_set_value(IMX_GPIO_NR(4, 9), 1);
>> + mdelay(50);
>> +}
>> +
>> +iomux_v3_cfg_t const usdhc1_pads[] = {
>> + MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
>> +};
>> +
>> +iomux_v3_cfg_t const usdhc2_pads[] = {
>> + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
>> +};
>> +
>> +
>> +static struct i2c_pads_info i2c_pad_info3 = {
>> + .scl = {
>> + .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
>> + .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(I2C_PAD_CTRL),
>> + .gp = IMX_GPIO_NR(3, 17)
>> + },
>> + .sda = {
>> + .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
>> + .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | MUX_PAD_CTRL(I2C_PAD_CTRL),
>> + .gp = IMX_GPIO_NR(3, 18)
>> + }
>> +};
>> +
>> +static void setup_iomux_uart(void)
>> +{
>> + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
>> + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
>> + imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
>> +}
>> +
>> +iomux_v3_cfg_t const pmic_pads[] = {
>> + MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
>> + MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
>> +};
>> +
>> +static void setup_pmic_pins(void)
>> +{
>> + imx_iomux_v3_setup_multiple_pads(pmic_pads, ARRAY_SIZE(pmic_pads));
>> +}
>> +
>> +iomux_v3_cfg_t const nand_pads[] = {
>> + MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> + MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> + MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> + MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> + MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> + MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> + MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> + MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> + MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> + MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> + MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> + MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> + MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> + MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> + MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
>> +};
>> +
>> +static void setup_nand_pins(void)
>> +{
>> + imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
>> +}
>> +
>> +#ifdef CONFIG_FSL_ESDHC
>> +struct fsl_esdhc_cfg usdhc_cfg[] = {
>> + {USDHC1_BASE_ADDR},
>> + {USDHC2_BASE_ADDR},
>> +};
>> +
>> +#define USDHC1_CD_GPIO IMX_GPIO_NR(6, 16)
>> +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
>> +
>> +int board_mmc_get_env_dev(int devno)
>> +{
>> + return devno - 1;
>> +}
>> +
>> +int board_mmc_getcd(struct mmc *mmc)
>> +{
>> + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
>> + int ret = 0;
>> +
>> + switch (cfg->esdhc_base) {
>> + case USDHC1_BASE_ADDR:
>> + ret = !gpio_get_value(USDHC1_CD_GPIO);
>> + break;
>> + case USDHC2_BASE_ADDR:
>> + ret = !gpio_get_value(USDHC2_CD_GPIO);
>> + break;
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +int board_mmc_init(bd_t *bis)
>> +{
>> + int ret;
>> + int i;
>> +
>> + /*
>> + * According to the board_mmc_init() the following map is done:
>> + * (U-Boot device node) (Physical Port)
>> + * mmc0 SOM
>> + * mmc1 Baseboard
>> + * mmc2 eMMC
>> + */
>> + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
>> + switch (i) {
>> + case 0:
>> + imx_iomux_v3_setup_multiple_pads(
>> + usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
>> + gpio_direction_input(USDHC1_CD_GPIO);
>> + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
>> + break;
>> + case 1:
>> + imx_iomux_v3_setup_multiple_pads(
>> + usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
>> + gpio_direction_input(USDHC2_CD_GPIO);
>> + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
>> + break;
>> + default:
>> + printf("Warning: you configured more USDHC controllers");
>> + printf("(%d) then supported by the board (%d)\n",
>> + i + 1, CONFIG_SYS_FSL_USDHC_NUM);
>> + return -EINVAL;
>> + }
>> +
>> + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
>> + if (ret)
>> + return ret;
>> + }
>> + return 0;
>> +}
>> +#endif
>> +
>> +int board_phy_config(struct phy_device *phydev)
>> +{
>> + if (phydev->drv->config)
>> + phydev->drv->config(phydev);
>> +
>> + return 0;
>> +}
>> +
>> +/*
>> + * Do not overwrite the console
>> + * Use always serial for U-Boot console
>> + */
>> +int overwrite_console(void)
>> +{
>> + return 1;
>> +}
>> +
>> +int board_eth_init(bd_t *bis)
>> +{
>> + setup_iomux_enet();
>> + return cpu_eth_init(bis);
>> +}
>> +
>> +int board_early_init_f(void)
>> +{
>> + setup_iomux_uart();
>> + setup_pmic_pins();
>> + setup_nand_pins();
>> + return 0;
>> +}
>> +
>> +int board_init(void)
>> +{
>> + /* address of boot parameters */
>> + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
>> +#ifdef CONFIG_FEC_MXC
>
> I think we should start to get rid of these annoying #ifdef. The board
> has always FEC, right ?
>
I find them annoying too, but I was trying to make this file flexible
and able to enable/disable features more easily. The System is broken
into two parts, the System on Module (SOM) and the baseboard. I'll
explain that in an updated patch ti give more background, but the
baseboards may have different options enabled and disabled but they
are all based on the same SOM. I am trying to start with adding
support for one board for now, but eventually, I hope to add more.
The idea here was to try to enable most things, but also make it easy
to remove them if they are not present.
>> + enable_fec_anatop_clock(0, ENET_50MHZ);
>> +#endif
>> +
[snip]
>
> Do you need the same thing as sabre ? If we check the name, more as
> "board_rev" this is a "soc_type". I know that the same is in sabre, I
> just ask if this is correct. It is like a misuse.
The initial support will support Dual and Quad. I borrowed this from
sabresd, but I prefer a switch statement, so I'm going to redo that.
Eventually, the next board introduced will support SOLO, so I'll add
those in as a future patch when I get the SOLO stuff completed.
Since the device trees are compatible between Quad and Dual, and
DualLite and Solo, I'll remove the board_rev stuff, but leave the
fdt_file stuff to make booting simpler.
>
>> + }
>> + else if (is_mx6dq()) {
>> + setenv("board_rev", "MX6Q");
>> + setenv("fdt_file", "imx6q-logicpd.dtb");
>> + }
>> + else if (is_mx6sdl()) {
>> + setenv("board_rev", "MX6DL");
>> + setenv("fdt_file", "imx6sdl-logicpd.dtb");
>> + }
>> + else if (is_mx6solo()) {
>> + setenv("board_rev", "MX6SOLO");
>> + setenv("fdt_file", "imx6sdl-logicpd.dtb");
>> + }
>> +#endif
>> + return 0;
>> +}
>> +
[snip]
>> --- /dev/null
>> +++ b/board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg
>> @@ -0,0 +1,217 @@
>> +/*
>> + * Copyright (C) 2017 Logic PD, Inc.
>> + * Adam Ford <aford173 at gmail.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + *
>> + * Refer doc/README.imximage for more details about how-to configure
>> + * and create imximage boot image
>> + *
>> + * The syntax is taken as close as possible with the kwbimage
>> + */
>> +
>> +/* image version */
>> +IMAGE_VERSION 2
>> +
>> +/*
>> + * Boot Device : sd or nand
>> + * nand: flash_offset: 0x0400
>> + * sd/mmc: flash_offset: 0x0400
>> + */
>> +
>> +/* the same flash_offset as sd */
>> +BOOT_FROM sd
>
> ...but I have read you boot from NAND, too. Something is not consistent.
This whole thing is confusing to me. I read the the README.imximage
file, but the vast majority of the boards used this context despite
being inconsistent with the readme. I think what I need to do is add:
#include <asm/imx-common/imximage.cfg>
BOOT_OFFSET FLASH_OFFSET_STANDARD
Is that correct?
[snip]
>> +//DATA 4 0x020e07a0 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B4DS
>> +//DATA 4 0x020e07a4 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B5DS
>> +//DATA 4 0x020e07a8 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B6DS
>> +//DATA 4 0x020e0748 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B7DS
>
> No dead code, please
>
Sorry about that. I took the output of the DDR Stress Test tool, and
did a massive find-replace. I ran the checkpatch script, but I think
it must ignore the .cfg file endings.
>
> Anyway, these are default values for DDR controller - why do you need ?
>
I am not sure what I need. Looking at bunch of boards, many of them
use similar settings. The README.imximage didn't explicitly say what
I need and don't need, and I am new to the i.MX6.
>> +
>> +DATA 4 0x020e05ac 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
>> +DATA 4 0x020e05b4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
>> +DATA 4 0x020e0528 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
>> +DATA 4 0x020e0520 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
>> +//DATA 4 0x020e0514 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4
>> +//DATA 4 0x020e0510 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5
>> +//DATA 4 0x020e05bc 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6
>> +//DATA 4 0x020e05c4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7
>> +
>> +
[snip]
>> +//For i.mx6qd parts of versions A & B (v1.0 v1.1) uncomment the following lines. For version C (v1.2) keep commented
>> +//DATA 4 0x021b08c0 0x24911492 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6
>> +//DATA 4 0x021b48c0 0x24911492
>
> ???
>
> If there something that depends on SOC version, it should be done in
> code by checking the HW revision and not hard-coding it into DCD.
>
Again, I just took the output of the stress test tool and used its
output. I'll remove the dead code.
>
>> +
>> +// Complete calibration by forced measurement:
>> +DATA 4 0x021b08b8 0x00000800 // DDR_PHY_P0_MPMUR0 frc_msr
>> +//DATA 4 0x021b48b8 0x00000800 // DDR_PHY_P0_MPMUR0 frc_msr
>
>
>> +//=============================================================================
>> +// Calibration setup end
>> +//=============================================================================
>> +
>> +//MMDC init:
>> +DATA 4 0x021b0004 0x00020036 // MMDC0_MDPDC
>> +DATA 4 0x021b0008 0x09444040 // MMDC0_MDOTC
>> +DATA 4 0x021b000c 0xB8BE7955 // MMDC0_MDCFG0
>> +DATA 4 0x021b0010 0xFF328F64 // MMDC0_MDCFG1
>> +DATA 4 0x021b0014 0x01FF00DB // MMDC0_MDCFG2
>> +
>> +//MDMISC: RALAT kept to the high level of 5.
>> +//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
>> +//a. better operation at low frequency for LPDDR2 freq < 100MHz change RALAT to 3
>> +//b. Small performence improvment
>> +DATA 4 0x021b0018 0x00011740 // MMDC0_MDMISC
>> +DATA 4 0x021b001c 0x00008000 // MMDC0_MDSCR set the Configuration request bit during MMDC set up
>> +DATA 4 0x021b002c 0x000026D2 // MMDC0_MDRWD
>> +DATA 4 0x021b0030 0x00BE1023 // MMDC0_MDOR
>> +DATA 4 0x021b0040 0x00000047 // Chan0 CS0_END
>> +DATA 4 0x021b0000 0x85190000 // MMDC0_MDCTL
>> +
>> +//Mode register writes
>> +DATA 4 0x021b001c 0x00888032 // MMDC0_MDSCR MR2 write CS0
>> +DATA 4 0x021b001c 0x00008033 // MMDC0_MDSCR MR3 write CS0
>> +DATA 4 0x021b001c 0x00008031 // MMDC0_MDSCR MR1 write CS0
>> +DATA 4 0x021b001c 0x19408030 // MMDC0_MDSCR MR0write CS0
>> +DATA 4 0x021b001c 0x04008040 // MMDC0_MDSCR ZQ calibration command sent to device on CS0
>> +
>> +//DATA 4 0x021b001c 0x0088803A // MMDC0_MDSCR MR2 write CS1
>> +//DATA 4 0x021b001c 0x0000803B // MMDC0_MDSCR MR3 write CS1
>> +//DATA 4 0x021b001c 0x00008039 // MMDC0_MDSCR MR1 write CS1
>> +//DATA 4 0x021b001c 0x19408038 // MMDC0_MDSCR MR0write CS1
>> +//DATA 4 0x021b001c 0x04008048 // MMDC0_MDSCR ZQ calibration command sent to device on CS1
>> +
>> +DATA 4 0x021b0020 0x00007800 // MMDC0_MDREF
>> +
>> +DATA 4 0x021b0818 0x00000007 // DDR_PHY_P0_MPODTCTRL
>> +//DATA 4 0x021b4818 0x00000007 // DDR_PHY_P1_MPODTCTRL
>> +
>> +DATA 4 0x021b0004 0x00025576 // MMDC0_MDPDC now SDCTL power down enabled
>> +
>> +DATA 4 0x021b0404 0x00011006 // MMDC0_MAPSR ADOPT power down enabled MMDC will enter automatically to self-refresh while the number of idle cycle reached.
>> +
>> +DATA 4 0x021b001c 0x00000000 // MMDC0_MDSCR clear this register (especially the configuration bit as initialization is complete)
>> +/* set the default clock gate to save power */
>> +DATA 4 0x020c4068 0x00C03F3F
>> +DATA 4 0x020c406c 0x0030FC03
>> +DATA 4 0x020c4070 0x0FFFC000
>> +DATA 4 0x020c4074 0x3FF00000
>> +DATA 4 0x020c4078 0xFFFFF300
>> +DATA 4 0x020c407c 0x0F0000F3
>> +DATA 4 0x020c4080 0x00000FFF
>> +
>
> I am still missing why we have to code this into the DCD instead of
> using the code provided by U-Boot. There are functions to setup the DDR
> controller and even (thanks to Marek !) for dynamic calibration. And
> yes, there are much more easy to maintain as these chunk of hexadecimal
> values.
>
I tried removing the two sections commented by "set the default clock
gate to save power" and
"enable AXI cache for VDOA/VPU/IPU" but U-Boot didn't show anything on
the screen. Is there some standard library or thing I need to
include? I see some boards use these sections and others do not, but
it's not clear to me as to why. I borrowed the concepts from SabreSD
and it uses these.
>
>> +/* enable AXI cache for VDOA/VPU/IPU */
>> +DATA 4 0x020e0010 0xF00000CF
>> +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
>> +DATA 4 0x020e0018 0x007F007F
>> +DATA 4 0x020e001c 0x007F007F
>
> Same here, it is normally part of common i.MX code.
[snip]
>
> Best regards,
> Stefano Babic
I very much appreciate your review and patience while I learn the
i.MX6. I'm going to work on the other comments from the others, but
if you have suggestions on how to avoid putting stuff into the DCD,
and the giant table, I'm very excited to try.
>
> --
> =====================================================================
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
> =====================================================================
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