[U-Boot] [PATCH v2 4/5] arm: socfpga: Move the FPGA driver header from arch/arm to include/
Chee, Tien Fong
tien.fong.chee at intel.com
Fri May 12 03:33:35 UTC 2017
On Kha, 2017-05-11 at 14:04 +0200, Marek Vasut wrote:
> On 05/11/2017 11:25 AM, tien.fong.chee at intel.com wrote:
> >
> > From: Tien Fong Chee <tien.fong.chee at intel.com>
> >
> > Move arch/arm FPGA driver header to include/intel_socfpga which
> > would be shared between arch platform drivers and FPGA drivers.
> Doesn't this patchset only add support for arria10 FPGA ? If so, this
> patch is pointless in the context of this patchset.
>
Arria10 FPGA header include fpga_manager.h as common header.There are
other headers depend on above common header. So that means they are all
related to each others. Hence this patch is needed to ensure all
related restructure properly before adding Arria10 FPGA driver.
> >
> > Signed-off-by: Tien Fong Chee <tien.fong.chee at intel.com>
> > ---
> > arch/arm/mach-socfpga/reset_manager_arria10.c | 2 +-
> > arch/arm/mach-socfpga/reset_manager_gen5.c | 5 +-
> > arch/arm/mach-socfpga/system_manager_gen5.c | 2 +-
> > drivers/ddr/altera/sdram.c | 5 +-
> > drivers/fpga/socfpga.c | 5 +-
> > drivers/fpga/socfpga_gen5.c | 2 +-
> > include/intel_socfpga/fpga_manager.h | 37 +++++++++++++++
> > include/intel_socfpga/fpga_manager_gen5.h | 68
> > +++++++++++++++++++++++++++
> > 8 files changed, 116 insertions(+), 10 deletions(-)
> > create mode 100644 include/intel_socfpga/fpga_manager.h
> > create mode 100644 include/intel_socfpga/fpga_manager_gen5.h
> >
> > diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c
> > b/arch/arm/mach-socfpga/reset_manager_arria10.c
> > index 66f1ec2..bfc375e 100644
> > --- a/arch/arm/mach-socfpga/reset_manager_arria10.c
> > +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
> > @@ -5,13 +5,13 @@
> > */
> >
> > #include <asm/io.h>
> > -#include <asm/arch/fpga_manager.h>
> > #include <asm/arch/misc.h>
> > #include <asm/arch/reset_manager.h>
> > #include <asm/arch/system_manager.h>
> > #include <common.h>
> > #include <errno.h>
> > #include <fdtdec.h>
> > +#include <intel_socfpga/fpga_manager.h>
> > #include <wait_bit.h>
> >
> > DECLARE_GLOBAL_DATA_PTR;
> > diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c
> > b/arch/arm/mach-socfpga/reset_manager_gen5.c
> > index aa88adb..3d76913 100644
> > --- a/arch/arm/mach-socfpga/reset_manager_gen5.c
> > +++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
> > @@ -1,13 +1,12 @@
> > /*
> > - * Copyright (C) 2013 Altera Corporation <www.altera.com>
> > + * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
> > *
> > * SPDX-License-Identifier: GPL-2.0+
> > */
> >
> > -
> > #include <common.h>
> > #include <asm/io.h>
> > -#include <asm/arch/fpga_manager.h>
> > +#include <intel_socfpga/fpga_manager.h>
> > #include <asm/arch/reset_manager.h>
> > #include <asm/arch/system_manager.h>
> >
> > diff --git a/arch/arm/mach-socfpga/system_manager_gen5.c
> > b/arch/arm/mach-socfpga/system_manager_gen5.c
> > index 3588a57..a32250b 100644
> > --- a/arch/arm/mach-socfpga/system_manager_gen5.c
> > +++ b/arch/arm/mach-socfpga/system_manager_gen5.c
> > @@ -7,7 +7,7 @@
> > #include <common.h>
> > #include <asm/io.h>
> > #include <asm/arch/system_manager.h>
> > -#include <asm/arch/fpga_manager.h>
> > +#include <intel_socfpga/fpga_manager.h>
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > diff --git a/drivers/ddr/altera/sdram.c
> > b/drivers/ddr/altera/sdram.c
> > index e74c5b0..0ff2549 100644
> > --- a/drivers/ddr/altera/sdram.c
> > +++ b/drivers/ddr/altera/sdram.c
> > @@ -1,13 +1,14 @@
> > /*
> > - * Copyright Altera Corporation (C) 2014-2015
> > + * Copyright Altera Corporation (C) 2014-2017
> > *
> > * SPDX-License-Identifier: GPL-2.0+
> > */
> > +
> > #include <common.h>
> > #include <errno.h>
> > #include <div64.h>
> > #include <watchdog.h>
> > -#include <asm/arch/fpga_manager.h>
> > +#include <intel_socfpga/fpga_manager.h>
> > #include <asm/arch/sdram.h>
> > #include <asm/arch/system_manager.h>
> > #include <asm/io.h>
> > diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
> > index d3633ea..4c9f238 100644
> > --- a/drivers/fpga/socfpga.c
> > +++ b/drivers/fpga/socfpga.c
> > @@ -8,7 +8,7 @@
> > #include <common.h>
> > #include <asm/io.h>
> > #include <linux/errno.h>
> > -#include <asm/arch/fpga_manager.h>
> > +#include <intel_socfpga/fpga_manager.h>
> > #include <asm/arch/reset_manager.h>
> > #include <asm/arch/system_manager.h>
> >
> > @@ -66,4 +66,5 @@ void fpgamgr_program_write(const void *rbf_data,
> > unsigned long rbf_size)
> > "3: nop\n"
> > : "+r"(src), "+r"(dst), "+r"(loops32),
> > "+r"(loops4) :
> > : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
> > "cc");
> > -}
> > \ No newline at end of file
> > +}
> > +
> > diff --git a/drivers/fpga/socfpga_gen5.c
> > b/drivers/fpga/socfpga_gen5.c
> > index 03285f8..743ed4d 100644
> > --- a/drivers/fpga/socfpga_gen5.c
> > +++ b/drivers/fpga/socfpga_gen5.c
> > @@ -8,7 +8,7 @@
> > #include <common.h>
> > #include <asm/io.h>
> > #include <linux/errno.h>
> > -#include <asm/arch/fpga_manager.h>
> > +#include <intel_socfpga/fpga_manager.h>
> > #include <asm/arch/reset_manager.h>
> > #include <asm/arch/system_manager.h>
> >
> > diff --git a/include/intel_socfpga/fpga_manager.h
> > b/include/intel_socfpga/fpga_manager.h
> > new file mode 100644
> > index 0000000..e02e4be
> > --- /dev/null
> > +++ b/include/intel_socfpga/fpga_manager.h
> > @@ -0,0 +1,37 @@
> > +/*
> > + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
> > + * All rights reserved.
> > + *
> > + * SPDX-License-Identifier: BSD-3-Clause
> > + */
> > +
> > +#ifndef _FPGA_MANAGER_H_
> > +#define _FPGA_MANAGER_H_
> > +
> > +#include <altera.h>
> > +
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > +#include <intel_socfpga/fpga_manager_gen5.h>
> > +#endif
> > +
> > +/* FPGA CD Ratio Value */
> > +#define CDRATIO_x1 0x0
> > +#define CDRATIO_x2 0x1
> > +#define CDRATIO_x4 0x2
> > +#define CDRATIO_x8 0x3
> > +
> > +/* SoCFPGA support functions */
> > +int fpgamgr_get_mode(void);
> > +int fpgamgr_poll_fpga_ready(void);
> > +void fpgamgr_program_write(const void *rbf_data, unsigned long
> > rbf_size);
> > +int fpgamgr_test_fpga_ready(void);;
> > +
> > +#define FPGA_TIMEOUT_CNT 0x1000000
> > +
> > +#ifndef __ASSEMBLY__
> > +
> > +/* Common prototypes */
> > +int fpgamgr_dclkcnt_set(unsigned long cnt);
> > +
> > +#endif /* __ASSEMBLY__ */
> > +#endif /* _FPGA_MANAGER_H_ */
> > diff --git a/include/intel_socfpga/fpga_manager_gen5.h
> > b/include/intel_socfpga/fpga_manager_gen5.h
> > new file mode 100644
> > index 0000000..2de7a11
> > --- /dev/null
> > +++ b/include/intel_socfpga/fpga_manager_gen5.h
> > @@ -0,0 +1,68 @@
> > +/*
> > + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
> > + * All rights reserved.
> > + *
> > + * SPDX-License-Identifier: BSD-3-Clause
> > + */
> > +
> > +#ifndef _FPGA_MANAGER_GEN5_H_
> > +#define _FPGA_MANAGER_GEN5_H_
> > +
> > +#define FPGAMGRREGS_STAT_MODE_MASK 0x7
> > +#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
> > +#define FPGAMGRREGS_STAT_MSEL_LSB 3
> > +
> > +#define FPGAMGRREGS_CTRL_CFGWDTH_MASK BIT(9)
> > +#define FPGAMGRREGS_CTRL_AXICFGEN_MASK BIT(8)
> > +#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK BIT(2)
> > +#define FPGAMGRREGS_CTRL_NCE_MASK BIT(1)
> > +#define FPGAMGRREGS_CTRL_EN_MASK BIT(0)
> > +#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
> > +
> > +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK BIT(3)
> > +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK BIT(2)
> > +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK BIT(1)
> > +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK BIT(0)
> > +
> > +/* FPGA Mode */
> > +#define FPGAMGRREGS_MODE_FPGAOFF 0x0
> > +#define FPGAMGRREGS_MODE_RESETPHASE 0x1
> > +#define FPGAMGRREGS_MODE_CFGPHASE 0x2
> > +#define FPGAMGRREGS_MODE_INITPHASE 0x3
> > +#define FPGAMGRREGS_MODE_USERMODE 0x4
> > +#define FPGAMGRREGS_MODE_UNKNOWN 0x5
> > +
> > +#ifndef __ASSEMBLY__
> > +
> > +struct socfpga_fpga_manager {
> > + /* FPGA Manager Module */
> > + u32 stat; /* 0x00 */
> > + u32 ctrl;
> > + u32 dclkcnt;
> > + u32 dclkstat;
> > + u32 gpo; /* 0x10 */
> > + u32 gpi;
> > + u32 misci; /* 0x18 */
> > + u32 _pad_0x1c_0x82c[517];
> > +
> > + /* Configuration Monitor (MON) Registers */
> > + u32 gpio_inten; /* 0x830 */
> > + u32 gpio_intmask;
> > + u32 gpio_inttype_level;
> > + u32 gpio_int_polarity;
> > + u32 gpio_intstatus; /* 0x840 */
> > + u32 gpio_raw_intstatus;
> > + u32 _pad_0x848;
> > + u32 gpio_porta_eoi;
> > + u32 gpio_ext_porta; /* 0x850 */
> > + u32 _pad_0x854_0x85c[3];
> > + u32 gpio_1s_sync; /* 0x860 */
> > + u32 _pad_0x864_0x868[2];
> > + u32 gpio_ver_id_code;
> > + u32 gpio_config_reg2; /* 0x870 */
> > + u32 gpio_config_reg1;
> > +};
> > +
> > +#endif /* __ASSEMBLY__ */
> > +
> > +#endif /* _FPGA_MANAGER_GEN5_H_ */
> >
>
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