[U-Boot] [PATCH v5 8/8] mx53: Add Board support for GE PPD
Stefano Babic
sbabic at denx.de
Thu Nov 9 09:31:44 UTC 2017
On 06/11/2017 20:14, Martyn Welch wrote:
> From: Peter Senna Tschudin <peter.senna at collabora.com>
>
> Create board support for GE PPD, based on mx53loco.
>
> Use mx53ppd_defconfig make target to configure for this board.
>
> Signed-off-by: Peter Senna Tschudin <peter.senna at collabora.com>
> Signed-off-by: Ian Ray <ian.ray at ge.com>
> Signed-off-by: Nandor Han <nandor.han at ge.com>
> Signed-off-by: Martyn Welch <martyn.welch at collabora.co.uk>
> Cc: Stefano Babic <sbabic at denx.de>
> ---
> Changes in v4:
> - Remove mach-type.h entry.
> - Move to ge board directory (to be able to use ge common code).
> - Remove now common VPD code.
> - Move do_lcd_enable() to mx53ppd_video.c.
>
> Changes in v5:
> - Reduced checkpatch warnings.
> - Simplified get_board_rev().
> - Propagated errors from clock_1GHz().
> - Simplified process_vpd().
> - Made check_time() and lcd_enable() static.
>
> arch/arm/mach-imx/mx5/Kconfig | 7 +
> board/ge/mx53ppd/Kconfig | 17 ++
> board/ge/mx53ppd/MAINTAINERS | 7 +
> board/ge/mx53ppd/Makefile | 12 +
> board/ge/mx53ppd/imximage.cfg | 87 ++++++++
> board/ge/mx53ppd/mx53ppd.c | 457 +++++++++++++++++++++++++++++++++++++++
> board/ge/mx53ppd/mx53ppd_video.c | 135 ++++++++++++
> board/ge/mx53ppd/ppd_gpio.h | 96 ++++++++
> configs/mx53ppd_defconfig | 39 ++++
> include/configs/mx53ppd.h | 248 +++++++++++++++++++++
> 10 files changed, 1105 insertions(+)
> create mode 100644 board/ge/mx53ppd/Kconfig
> create mode 100644 board/ge/mx53ppd/MAINTAINERS
> create mode 100644 board/ge/mx53ppd/Makefile
> create mode 100644 board/ge/mx53ppd/imximage.cfg
> create mode 100644 board/ge/mx53ppd/mx53ppd.c
> create mode 100644 board/ge/mx53ppd/mx53ppd_video.c
> create mode 100644 board/ge/mx53ppd/ppd_gpio.h
> create mode 100644 configs/mx53ppd_defconfig
> create mode 100644 include/configs/mx53ppd.h
>
> diff --git a/arch/arm/mach-imx/mx5/Kconfig b/arch/arm/mach-imx/mx5/Kconfig
> index ef37c35..02adace 100644
> --- a/arch/arm/mach-imx/mx5/Kconfig
> +++ b/arch/arm/mach-imx/mx5/Kconfig
> @@ -45,6 +45,12 @@ config TARGET_MX53LOCO
> select BOARD_LATE_INIT
> select MX53
>
> +config TARGET_MX53PPD
> + bool "Support mx53ppd"
> + select MX53
> + help
> + Enable support for the GE Healthcare PPD.
> +
> config TARGET_MX53SMD
> bool "Support mx53smd"
> select MX53
> @@ -70,6 +76,7 @@ source "board/freescale/mx53ard/Kconfig"
> source "board/freescale/mx53evk/Kconfig"
> source "board/freescale/mx53loco/Kconfig"
> source "board/freescale/mx53smd/Kconfig"
> +source "board/ge/mx53ppd/Kconfig"
> source "board/inversepath/usbarmory/Kconfig"
> source "board/technologic/ts4800/Kconfig"
>
> diff --git a/board/ge/mx53ppd/Kconfig b/board/ge/mx53ppd/Kconfig
> new file mode 100644
> index 0000000..781c1cf
> --- /dev/null
> +++ b/board/ge/mx53ppd/Kconfig
> @@ -0,0 +1,17 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +
> +if TARGET_MX53PPD
> +
> +config SYS_BOARD
> + default "mx53ppd"
> +
> +config SYS_VENDOR
> + default "ge"
> +
> +config SYS_SOC
> + default "mx5"
> +
> +config SYS_CONFIG_NAME
> + default "mx53ppd"
> +
> +endif
> diff --git a/board/ge/mx53ppd/MAINTAINERS b/board/ge/mx53ppd/MAINTAINERS
> new file mode 100644
> index 0000000..9b64b5d
> --- /dev/null
> +++ b/board/ge/mx53ppd/MAINTAINERS
> @@ -0,0 +1,7 @@
> +MX53PPD BOARD
> +M: Antti Mäentausta <antti.maentausta at ge.com>
> +M: Martyn Welch <martyn.welch at collabora.co.uk>
> +S: Maintained
> +F: board/freescale/mx53ppd/
> +F: include/configs/mx53ppd.h
> +F: configs/mx53ppd_defconfig
> diff --git a/board/ge/mx53ppd/Makefile b/board/ge/mx53ppd/Makefile
> new file mode 100644
> index 0000000..928edfb
> --- /dev/null
> +++ b/board/ge/mx53ppd/Makefile
> @@ -0,0 +1,12 @@
> +# Copyright 2017 General Electric Company
> +#
> +# Based on board/freescale/mx53loco/Makefile:
> +#
> +# (C) Copyright 2011 Freescale Semiconductor, Inc.
> +# Jason Liu <r64343 at freescale.com>
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y += mx53ppd.o
> +obj-$(CONFIG_VIDEO) += mx53ppd_video.o
> diff --git a/board/ge/mx53ppd/imximage.cfg b/board/ge/mx53ppd/imximage.cfg
> new file mode 100644
> index 0000000..83ff4b8
> --- /dev/null
> +++ b/board/ge/mx53ppd/imximage.cfg
> @@ -0,0 +1,87 @@
> +/*
> + * Copyright 2017 General Electric Company
> + *
> + * Based on board/freescale/mx53loco/imximage.cfg:
> + *
> + * Copyright (C) 2011 Freescale Semiconductor, Inc.
> + * Jason Liu <r64343 at freescale.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + *
> + * Refer doc/README.imximage for more details about how-to configure
> + * and create imximage boot image
> + *
> + * The syntax is taken as close as possible with the kwbimage
> + */
> +
> +/* image version */
> +IMAGE_VERSION 2
> +
> +/*
> + * Boot Device : one of
> + * spi, sd (the board has no nand neither onenand)
> + */
> +BOOT_FROM sd
> +
> +/*
> + * Device Configuration Data (DCD)
> + *
> + * Each entry must have the format:
> + * Addr-type Address Value
> + *
> + * where:
> + * Addr-type register length (1,2 or 4 bytes)
> + * Address absolute address of the register
> + * value value to be stored in the register
> + */
> +DATA 4 0x53fa8004 0x00194005
> +DATA 4 0x53fa8554 0x00300000
> +DATA 4 0x53fa8558 0x00300040
> +DATA 4 0x53fa8560 0x00300000
> +DATA 4 0x53fa8564 0x00300040
> +DATA 4 0x53fa8568 0x00300040
> +DATA 4 0x53fa8570 0x00300000
> +DATA 4 0x53fa8574 0x00300000
> +DATA 4 0x53fa8578 0x00300000
> +DATA 4 0x53fa857c 0x00300040
> +DATA 4 0x53fa8580 0x00300040
> +DATA 4 0x53fa8584 0x00300000
> +DATA 4 0x53fa8588 0x00300000
> +DATA 4 0x53fa8590 0x00300040
> +DATA 4 0x53fa8594 0x00300000
> +DATA 4 0x53fa86f0 0x00300000
> +DATA 4 0x53fa86f4 0x00000000
> +DATA 4 0x53fa86fc 0x00000000
> +DATA 4 0x53fa8714 0x00000000
> +DATA 4 0x53fa8718 0x00300000
> +DATA 4 0x53fa871c 0x00300000
> +DATA 4 0x53fa8720 0x00300000
> +DATA 4 0x53fa8728 0x00300000
> +DATA 4 0x53fa872c 0x00300000
> +DATA 4 0x63fd9088 0x35343535
> +DATA 4 0x63fd9090 0x4d444c44
> +DATA 4 0x63fd907c 0x01370138
> +DATA 4 0x63fd9080 0x013b013c
> +DATA 4 0x63fd9018 0x00111740
> +DATA 4 0x63fd9000 0x85190000
> +DATA 4 0x63fd900c 0x8b8f52e3
> +DATA 4 0x63fd9010 0xb68e8a63
> +DATA 4 0x63fd9014 0x01ff00db
> +DATA 4 0x63fd902c 0x000026d2
> +DATA 4 0x63fd9030 0x008f0e21
> +DATA 4 0x63fd9008 0x09333030
> +DATA 4 0x63fd9004 0x0002002d
> +DATA 4 0x63fd901c 0x00008032
> +DATA 4 0x63fd901c 0x00008033
> +DATA 4 0x63fd901c 0x00468031
> +DATA 4 0x63fd901c 0x052080b0
> +DATA 4 0x63fd901c 0x04008040
> +DATA 4 0x63fd901c 0x0000803a
> +DATA 4 0x63fd901c 0x0000803b
> +DATA 4 0x63fd901c 0x00028039
> +DATA 4 0x63fd901c 0x05208138
> +DATA 4 0x63fd901c 0x04008048
> +DATA 4 0x63fd9020 0x00005800
> +DATA 4 0x63fd9040 0x05380003
> +DATA 4 0x63fd9058 0x00011110
> +DATA 4 0x63fd901c 0x00000000
> diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c
> new file mode 100644
> index 0000000..6a8a29d
> --- /dev/null
> +++ b/board/ge/mx53ppd/mx53ppd.c
> @@ -0,0 +1,457 @@
> +/*
> + * Copyright 2017 General Electric Company
> + *
> + * Based on board/freescale/mx53loco/mx53loco.c:
> + *
> + * Copyright (C) 2011 Freescale Semiconductor, Inc.
> + * Jason Liu <r64343 at freescale.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/arch/crm_regs.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/iomux-mx53.h>
> +#include <asm/arch/clock.h>
> +#include <linux/errno.h>
> +#include <asm/mach-imx/mxc_i2c.h>
> +#include <asm/mach-imx/mx5_video.h>
> +#include <netdev.h>
> +#include <i2c.h>
> +#include <mmc.h>
> +#include <fsl_esdhc.h>
> +#include <asm/gpio.h>
> +#include <power/pmic.h>
> +#include <dialog_pmic.h>
> +#include <fsl_pmic.h>
> +#include <linux/fb.h>
> +#include <ipu_pixfmt.h>
> +#include <watchdog.h>
> +#include "ppd_gpio.h"
> +#include <stdlib.h>
> +#include "../../ge/common/vpd_reader.h"
> +#include <rtc.h>
> +
> +#define MX53PPD_LCD_POWER IMX_GPIO_NR(3, 24)
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/* Index of I2C1, SEGMENT 1 (see CONFIG_SYS_I2C_BUSES). */
> +#define VPD_EEPROM_BUS 2
> +
> +/* Address of 24C08 EEPROM. */
> +#define VPD_EEPROM_ADDR 0x50
> +#define VPD_EEPROM_ADDR_LEN 1
> +
> +static u32 mx53_dram_size[2];
> +
> +phys_size_t get_effective_memsize(void)
> +{
> + /*
> + * WARNING: We must override get_effective_memsize() function here
> + * to report only the size of the first DRAM bank. This is to make
> + * U-Boot relocator place U-Boot into valid memory, that is, at the
> + * end of the first DRAM bank. If we did not override this function
> + * like so, U-Boot would be placed at the address of the first DRAM
> + * bank + total DRAM size - sizeof(uboot), which in the setup where
> + * each DRAM bank contains 512MiB of DRAM would result in placing
> + * U-Boot into invalid memory area close to the end of the first
> + * DRAM bank.
> + */
> + return mx53_dram_size[0];
> +}
> +
> +int dram_init(void)
> +{
> + mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
> + mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
> +
> + gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
> +
> + return 0;
> +}
> +
> +int dram_init_banksize(void)
> +{
> + gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
> + gd->bd->bi_dram[0].size = mx53_dram_size[0];
> +
> + gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
> + gd->bd->bi_dram[1].size = mx53_dram_size[1];
> +
> + return 0;
> +}
> +
> +u32 get_board_rev(void)
> +{
> + return get_cpu_rev() & ~(0xF << 8);
> +}
> +
> +#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
> + PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
> +
> +#ifdef CONFIG_USB_EHCI_MX5
> +int board_ehci_hcd_init(int port)
> +{
> + /* request VBUS power enable pin, GPIO7_8 */
> + imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
> + gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
> + return 0;
> +}
> +#endif
> +
> +static void setup_iomux_fec(void)
> +{
> + static const iomux_v3_cfg_t fec_pads[] = {
> + NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
> + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP |
> + PAD_CTL_ODE),
> + NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
> + NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
> + PAD_CTL_HYS | PAD_CTL_PKE),
> + NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
> + PAD_CTL_HYS | PAD_CTL_PKE),
> + NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
> + NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
> + NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
> + NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
> + PAD_CTL_HYS | PAD_CTL_PKE),
> + NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
> + PAD_CTL_HYS | PAD_CTL_PKE),
> + NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
> + PAD_CTL_HYS | PAD_CTL_PKE),
> + };
> +
> + imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
> +}
> +
> +#ifdef CONFIG_FSL_ESDHC
> +struct fsl_esdhc_cfg esdhc_cfg[2] = {
> + {MMC_SDHC3_BASE_ADDR},
> + {MMC_SDHC1_BASE_ADDR},
> +};
> +
> +int board_mmc_getcd(struct mmc *mmc)
> +{
> + return 1;
> +}
> +
> +#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
> + PAD_CTL_PUS_100K_UP)
> +#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
> + PAD_CTL_DSE_HIGH)
> +
> +int board_mmc_init(bd_t *bis)
> +{
> + static const iomux_v3_cfg_t sd1_pads[] = {
> + NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
> + SD_CMD_PAD_CTRL),
> + NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
> + NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
> + NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
> + NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
> + NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
> + NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
> + NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
> + NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
> + NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
> + MX53_PAD_EIM_DA11__GPIO3_11,
> + };
> +
> + static const iomux_v3_cfg_t sd2_pads[] = {
> + NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
> + NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
> + NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
> + NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
> + NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
> + NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
> + MX53_PAD_EIM_DA13__GPIO3_13,
> + };
> +
> + u32 index;
> + int ret;
> +
> + esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
> + esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
> +
> + for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
> + switch (index) {
> + case 0:
> + imx_iomux_v3_setup_multiple_pads(sd1_pads,
> + ARRAY_SIZE(sd1_pads));
> + break;
> + case 1:
> + imx_iomux_v3_setup_multiple_pads(sd2_pads,
> + ARRAY_SIZE(sd2_pads));
> + break;
> + default:
> + printf("Warning: you configured more ESDHC controller (%d) as supported by the board(2)\n",
> + CONFIG_SYS_FSL_ESDHC_NUM);
> + return -EINVAL;
> + }
> + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +#endif
> +
> +#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
> + PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
> +
> +static void setup_iomux_i2c(void)
> +{
> + static const iomux_v3_cfg_t i2c1_pads[] = {
> + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
> + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
> + };
> +
> + imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
> +}
> +
> +#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
> +
> +static struct i2c_pads_info i2c_pad_info1 = {
> + .scl = {
> + .i2c_mode = MX53_PAD_EIM_D21__I2C1_SCL | I2C_PAD,
> + .gpio_mode = MX53_PAD_EIM_D28__GPIO3_28 | I2C_PAD,
> + .gp = IMX_GPIO_NR(3, 28)
> + },
> + .sda = {
> + .i2c_mode = MX53_PAD_EIM_D28__I2C1_SDA | I2C_PAD,
> + .gpio_mode = MX53_PAD_EIM_D21__GPIO3_21 | I2C_PAD,
> + .gp = IMX_GPIO_NR(3, 21)
> + }
> +};
> +
> +static int clock_1GHz(void)
> +{
> + int ret;
> + u32 ref_clk = MXC_HCLK;
> + /*
> + * After increasing voltage to 1.25V, we can switch
> + * CPU clock to 1GHz and DDR to 400MHz safely
> + */
> + ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
> + if (ret) {
> + printf("CPU: Switch CPU clock to 1GHZ failed\n");
> + return -1;
> + }
> +
> + ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
> + ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
> + if (ret) {
> + printf("CPU: Switch DDR clock to 400MHz failed\n");
> + return -1;
> + }
> +
> + return 0;
> +}
> +
> +void ppd_gpio_init(void)
> +{
> + int i;
> +
> + imx_iomux_v3_setup_multiple_pads(ppd_pads, ARRAY_SIZE(ppd_pads));
> + for (i = 0; i < ARRAY_SIZE(ppd_gpios); ++i)
> + gpio_direction_output(ppd_gpios[i].gpio, ppd_gpios[i].value);
> +}
> +
> +int board_early_init_f(void)
> +{
> + setup_iomux_fec();
> + setup_iomux_lcd();
> + ppd_gpio_init();
> +
> + return 0;
> +}
> +
> +/*
> + * Do not overwrite the console
> + * Use always serial for U-Boot console
> + */
> +int overwrite_console(void)
> +{
> + return 1;
> +}
> +
> +#define VPD_TYPE_INVALID 0x00
> +#define VPD_BLOCK_NETWORK 0x20
> +#define VPD_BLOCK_HWID 0x44
> +#define VPD_PRODUCT_PPD 4
> +#define VPD_HAS_MAC1 0x1
> +#define VPD_MAC_ADDRESS_LENGTH 6
> +
> +struct vpd_cache {
> + u8 product_id;
> + u8 has;
> + unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
> +};
> +
> +/*
> + * Extracts MAC and product information from the VPD.
> + */
> +static int vpd_callback(void *userdata, u8 id, u8 version, u8 type, size_t size,
> + u8 const *data)
> +{
> + struct vpd_cache *vpd = (struct vpd_cache *)userdata;
> +
> + if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
> + size >= 1) {
> + vpd->product_id = data[0];
> +
> + } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
> + type != VPD_TYPE_INVALID) {
> + if (size >= 6) {
> + vpd->has |= VPD_HAS_MAC1;
> + memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
> + }
> + }
> +
> + return 0;
> +}
> +
> +static void process_vpd(struct vpd_cache *vpd)
> +{
> + int fec_index = -1;
> +
> + if (vpd->product_id == VPD_PRODUCT_PPD)
> + fec_index = 0;
> +
> + if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1))
> + eth_env_set_enetaddr("ethaddr", vpd->mac1);
> +}
> +
> +static int read_vpd(uint eeprom_bus)
> +{
> + struct vpd_cache vpd;
> + int res;
> + int size = 1024;
> + u8 *data;
> + unsigned int current_i2c_bus = i2c_get_bus_num();
> +
> + res = i2c_set_bus_num(eeprom_bus);
> + if (res < 0)
> + return res;
> +
> + data = malloc(size);
> + if (!data)
> + return -ENOMEM;
> +
> + res = i2c_read(VPD_EEPROM_ADDR, 0, VPD_EEPROM_ADDR_LEN, data, size);
> + if (res == 0) {
> + memset(&vpd, 0, sizeof(vpd));
> + vpd_reader(size, data, &vpd, vpd_callback);
> + process_vpd(&vpd);
> + }
> +
> + free(data);
> +
> + i2c_set_bus_num(current_i2c_bus);
> + return res;
> +}
> +
> +static void check_time(void)
> +{
> + int ret, i;
> + struct rtc_time tm;
> + u8 retry = 3;
> +
> + unsigned int current_i2c_bus = i2c_get_bus_num();
> +
> + ret = i2c_set_bus_num(CONFIG_SYS_RTC_BUS_NUM);
> + if (ret < 0)
> + return;
> +
> + rtc_init();
> +
> + for (i = 0; i < retry; i++) {
> + ret = rtc_get(&tm);
> + if (!ret || ret == -EINVAL)
> + break;
> + }
> +
> + if (ret < 0)
> + env_set("rtc_status", "RTC_ERROR");
> +
> + if (tm.tm_year > 2037) {
> + tm.tm_sec = 0;
> + tm.tm_min = 0;
> + tm.tm_hour = 0;
> + tm.tm_mday = 1;
> + tm.tm_wday = 2;
> + tm.tm_mon = 1;
> + tm.tm_year = 2036;
> +
> + for (i = 0; i < retry; i++) {
> + ret = rtc_set(&tm);
> + if (!ret)
> + break;
> + }
> +
> + if (ret < 0)
> + env_set("rtc_status", "RTC_ERROR");
> + }
> +
> + i2c_set_bus_num(current_i2c_bus);
> +}
> +
> +int board_init(void)
> +{
> + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
> +
> + mxc_set_sata_internal_clock();
> + setup_iomux_i2c();
> +
> + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
> +
> + return 0;
> +}
> +
> +int misc_init_r(void)
> +{
> + const char *cause;
> +
> + /* We care about WDOG only, treating everything else as
> + * a power-on-reset.
> + */
> + if (get_imx_reset_cause() & 0x0010)
> + cause = "WDOG";
> + else
> + cause = "POR";
> +
> + env_set("bootcause", cause);
> +
> + return 0;
> +}
> +
> +int board_late_init(void)
> +{
> + int res;
> +
> + read_vpd(VPD_EEPROM_BUS);
> +
> + res = clock_1GHz();
> + if (res != 0)
> + return res;
> +
> + print_cpuinfo();
> + hw_watchdog_init();
> +
> + check_time();
> +
> + return 0;
> +}
> +
> +int checkboard(void)
> +{
> + puts("Board: GE PPD\n");
> +
> + return 0;
> +}
> diff --git a/board/ge/mx53ppd/mx53ppd_video.c b/board/ge/mx53ppd/mx53ppd_video.c
> new file mode 100644
> index 0000000..45974bc
> --- /dev/null
> +++ b/board/ge/mx53ppd/mx53ppd_video.c
> @@ -0,0 +1,135 @@
> +/*
> + * Copyright 2017 General Electric Company
> + *
> + * Based on board/freescale/mx53loco/mx53loco_video.c:
> + *
> + * Copyright (C) 2012 Freescale Semiconductor, Inc.
> + * Fabio Estevam <fabio.estevam at freescale.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <linux/list.h>
> +#include <asm/gpio.h>
> +#include <asm/arch/iomux-mx53.h>
> +#include <linux/fb.h>
> +#include <ipu_pixfmt.h>
> +#include <asm/arch/crm_regs.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/io.h>
> +#include <pwm.h>
> +#include "ppd_gpio.h"
> +
> +#define MX53PPD_LCD_POWER IMX_GPIO_NR(3, 24)
> +
> +static struct fb_videomode const nv_spwg = {
> + .name = "NV-SPWGRGB888",
> + .refresh = 60,
> + .xres = 800,
> + .yres = 480,
> + .pixclock = 15384,
> + .left_margin = 16,
> + .right_margin = 210,
> + .upper_margin = 10,
> + .lower_margin = 22,
> + .hsync_len = 30,
> + .vsync_len = 13,
> + .sync = FB_SYNC_EXT,
> + .vmode = FB_VMODE_NONINTERLACED
> +};
> +
> +void setup_iomux_lcd(void)
> +{
> + static const iomux_v3_cfg_t lcd_pads[] = {
> + MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
> + MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
> + MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
> + MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
> + MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
> + MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
> + MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
> + MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
> + MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
> + MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
> + MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
> + MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
> + MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
> + MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
> + MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
> + MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
> + MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
> + MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
> + MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
> + MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
> + MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
> + MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
> + MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
> + MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
> + MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
> + MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
> + MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
> + MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
> + };
> +
> + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
> +}
> +
> +static void lcd_enable(void)
> +{
> + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
> +
> + /* Set LDB_DI0 as clock source for IPU_DI0 */
> + clrsetbits_le32(&mxc_ccm->cscmr2,
> + MXC_CCM_CSCMR2_DI0_CLK_SEL_MASK,
> + MXC_CCM_CSCMR2_DI0_CLK_SEL(
> + MXC_CCM_CSCMR2_DI0_CLK_SEL_LDB_DI0_CLK));
> +
> + /* Turn on IPU LDB DI0 clocks */
> + setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_LDB_DI0(3));
> +
> + /* Turn on IPU DI0 clocks */
> + setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_IPU_DI0(3));
> +
> + /* Configure LDB */
> + writel(IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
> + IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
> + IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
> + &iomux->gpr[2]);
> +
> + /* Enable backlights */
> + pwm_init(1, 0, 0);
> +
> + /* duty cycle 5000000ns, period: 5000000ns */
> + pwm_config(1, 5000000, 5000000);
> +
> + /* Backlight Power */
> + gpio_direction_output(BACKLIGHT_ENABLE, 1);
> +
> + pwm_enable(1);
> +}
> +
> +static int do_lcd_enable(cmd_tbl_t *cmdtp, int flag, int argc,
> + char * const argv[])
> +{
> + lcd_enable();
> + return 0;
> +}
> +
> +U_BOOT_CMD(
> + ppd_lcd_enable, 1, 1, do_lcd_enable,
> + "enable PPD LCD",
> + "no parameters"
> +);
> +
> +int board_video_skip(void)
> +{
> + int ret;
> +
> + ret = ipuv3_fb_init(&nv_spwg, 0, IPU_PIX_FMT_RGB24);
> + if (ret)
> + printf("Display cannot be configured: %d\n", ret);
> +
> + return ret;
> +}
> diff --git a/board/ge/mx53ppd/ppd_gpio.h b/board/ge/mx53ppd/ppd_gpio.h
> new file mode 100644
> index 0000000..71a88a1
> --- /dev/null
> +++ b/board/ge/mx53ppd/ppd_gpio.h
> @@ -0,0 +1,96 @@
> +/*
> + * (C) Copyright 2015 General Electric Company
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __PPD_GPIO_H_
> +#define __PPD_GPIO_H_
> +
> +#include <asm/arch/iomux-mx53.h>
> +#include <asm/gpio.h>
> +
> +#define PPD_UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
> + PAD_CTL_PUS_100K_UP)
> +
> +static const iomux_v3_cfg_t ppd_pads[] = {
> + /* FEC */
> + MX53_PAD_EIM_A22__GPIO2_16,
> + /* UART */
> + NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__UART1_RXD_MUX, PPD_UART_PAD_CTRL),
> + NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__UART1_TXD_MUX, PPD_UART_PAD_CTRL),
> + /* Video */
> + MX53_PAD_CSI0_DATA_EN__GPIO5_20, /* LR_SCAN_CTRL */
> + MX53_PAD_CSI0_VSYNC__GPIO5_21, /* UD_SCAN_CTRL */
> + MX53_PAD_CSI0_DAT10__GPIO5_28, /* DATA_WIDTH_CTRL */
> + MX53_PAD_CSI0_PIXCLK__GPIO5_18, /* HOST_CONTROLLED_RESET_TO_LCD_N */
> + MX53_PAD_EIM_DA2__GPIO3_2, /* LVDS1_MUX_CTRL */
> + MX53_PAD_EIM_DA3__GPIO3_3, /* LVDS0_MUX_CTRL */
> + MX53_PAD_EIM_A21__GPIO2_17, /* ENABLE_PWR_TO_LCD_AND_UI_INTERFACE */
> + MX53_PAD_CSI0_DAT11__GPIO5_29, /* BACKLIGHT_ENABLE */
> + MX53_PAD_DISP0_DAT9__PWM2_PWMO, /* IMX535_PWM2_TO_LCD_CONNECTOR */
> + /* I2C */
> + MX53_PAD_EIM_A20__GPIO2_18, /* RESET_I2C1_BUS_SEGMENT_MUX_N */
> +
> + /* SPI */
> + MX53_PAD_DISP0_DAT23__GPIO5_17,
> + MX53_PAD_KEY_COL2__GPIO4_10,
> + MX53_PAD_KEY_ROW2__GPIO4_11,
> + MX53_PAD_KEY_COL3__GPIO4_12,
> +};
> +
> +struct gpio_cfg {
> + unsigned int gpio;
> + int value;
> +};
> +
> +#define RESET_IMX535_ETHERNET_PHY_N IMX_GPIO_NR(2, 16)
> +#define UD_SCAN_CTRL IMX_GPIO_NR(5, 21)
> +#define LR_SCAN_CTRL IMX_GPIO_NR(5, 20)
> +#define LVDS0_MUX_CTRL IMX_GPIO_NR(3, 3)
> +#define LVDS1_MUX_CTRL IMX_GPIO_NR(3, 2)
> +#define HOST_CONTROLLED_RESET_TO_LCD_N IMX_GPIO_NR(5, 18)
> +#define DATA_WIDTH_CTRL IMX_GPIO_NR(5, 28)
> +#define RESET_DP0_TRANSMITTER_N IMX_GPIO_NR(2, 28)
> +#define RESET_DP1_TRANSMITTER_N IMX_GPIO_NR(2, 29)
> +#define POWER_DOWN_LVDS0_DESERIALIZER_N IMX_GPIO_NR(2, 22)
> +#define POWER_DOWN_LVDS1_DESERIALIZER_N IMX_GPIO_NR(2, 27)
> +#define ENABLE_PWR_TO_LCD_AND_UI_INTERFACE IMX_GPIO_NR(2, 17)
> +#define BACKLIGHT_ENABLE IMX_GPIO_NR(5, 29)
> +#define RESET_I2C1_BUS_SEGMENT_MUX_N IMX_GPIO_NR(2, 18)
> +#define ECSPI1_CS0 IMX_GPIO_NR(5, 17)
> +#define ECSPI1_CS1 IMX_GPIO_NR(4, 10)
> +#define ECSPI1_CS2 IMX_GPIO_NR(4, 11)
> +#define ECSPI1_CS3 IMX_GPIO_NR(4, 12)
> +
> +static const struct gpio_cfg ppd_gpios[] = {
> + /* FEC */
> + /* Drive Low as GPIO output for 25ms per Eth Phy IX spec */
> + /* Then Drive High as GPIO output to bring Eth Phy IC out of reset */
> + { RESET_IMX535_ETHERNET_PHY_N, 0 },
> + { RESET_IMX535_ETHERNET_PHY_N, 1 },
> + /* Video */
> + { UD_SCAN_CTRL, 0 },
> + { LR_SCAN_CTRL, 1 },
> +#ifdef PROPRIETARY_CHANGES
> + { LVDS0_MUX_CTRL, 1 },
> +#else
> + { LVDS0_MUX_CTRL, 0 },
> +#endif
> + { LVDS1_MUX_CTRL, 1 },
> + { HOST_CONTROLLED_RESET_TO_LCD_N, 1 },
> + { DATA_WIDTH_CTRL, 0 },
> + { RESET_DP0_TRANSMITTER_N, 1 },
> + { RESET_DP1_TRANSMITTER_N, 1 },
> + { POWER_DOWN_LVDS0_DESERIALIZER_N, 1 },
> + { POWER_DOWN_LVDS1_DESERIALIZER_N, 1 },
> + { ENABLE_PWR_TO_LCD_AND_UI_INTERFACE, 1 },
> + { BACKLIGHT_ENABLE, 0 },
> + { RESET_I2C1_BUS_SEGMENT_MUX_N, 1 },
> + { ECSPI1_CS0, 1 },
> + { ECSPI1_CS1, 1 },
> + { ECSPI1_CS2, 1 },
> + { ECSPI1_CS3, 1 },
> +};
> +
> +#endif /* __PPD_GPIO_H_ */
> diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig
> new file mode 100644
> index 0000000..0ab19e9
> --- /dev/null
> +++ b/configs/mx53ppd_defconfig
> @@ -0,0 +1,39 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_MX5=y
> +CONFIG_TARGET_MX53PPD=y
> +CONFIG_FIT=y
> +CONFIG_BOOTCOUNT=y
> +CONFIG_BOOTCOUNT_EXT=y
> +CONFIG_SYS_BOOTCOUNT_EXT_INTERFACE="mmc"
> +CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="0:5"
> +CONFIG_SYS_BOOTCOUNT_EXT_NAME="/boot/failures"
> +CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000
> +CONFIG_NETDEVICES=y
> +CONFIG_VIDEO=y
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ge/mx53ppd/imximage.cfg"
> +CONFIG_BOOTDELAY=1
> +# CONFIG_CONSOLE_MUX is not set
> +CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
> +CONFIG_DISPLAY_CPUINFO=y
> +CONFIG_HUSH_PARSER=y
> +CONFIG_CMD_BOOTZ=y
> +CONFIG_CMD_I2C=y
> +CONFIG_RTC_S35392A=y
> +# CONFIG_CMD_IMLS is not set
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_USB=y
> +CONFIG_CMD_DHCP=y
> +CONFIG_CMD_MII=y
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_EXT2=y
> +CONFIG_CMD_EXT4=y
> +CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_CMD_FAT=y
> +CONFIG_CMD_FS_GENERIC=y
> +CONFIG_USB=y
> +CONFIG_USB_STORAGE=y
> +# CONFIG_VIDEO_SW_CURSOR is not set
> +CONFIG_OF_LIBFDT=y
> +
> +CONFIG_MMC=y
> diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h
> new file mode 100644
> index 0000000..92dd845
> --- /dev/null
> +++ b/include/configs/mx53ppd.h
> @@ -0,0 +1,248 @@
> +/*
> + * Copyright (C) 2011 Freescale Semiconductor, Inc.
> + * Jason Liu <r64343 at freescale.com>
> + *
> + * Configuration settings for Freescale MX53 low cost board.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#include <asm/arch/imx-regs.h>
> +
> +#define CONSOLE_DEV "ttymxc0"
> +
> +#define CONFIG_CMDLINE_TAG
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_INITRD_TAG
> +
> +#define CONFIG_SYS_FSL_CLK
> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
> +
> +#define CONFIG_HW_WATCHDOG
> +#define CONFIG_IMX_WATCHDOG
> +#define CONFIG_WATCHDOG_TIMEOUT_MSECS 8000
> +
> +#define CONFIG_MISC_INIT_R
> +#define CONFIG_BOARD_LATE_INIT
> +#define CONFIG_MXC_GPIO
> +#define CONFIG_REVISION_TAG
> +
> +#define CONFIG_MXC_UART
> +#define CONFIG_MXC_UART_BASE UART1_BASE
> +
> +/* MMC Configs */
> +#define CONFIG_FSL_ESDHC
> +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> +#define CONFIG_SYS_FSL_ESDHC_NUM 2
> +
> +#define CONFIG_SUPPORT_RAW_INITRD /* bootz raw initrd support */
> +
> +/* Eth Configs */
> +#define CONFIG_MII
> +
> +#define CONFIG_FEC_MXC
> +#define IMX_FEC_BASE FEC_BASE_ADDR
> +#define CONFIG_FEC_MXC_PHYADDR 0x1F
> +
> +/* USB Configs */
> +#define CONFIG_USB_EHCI_MX5
> +#define CONFIG_USB_HOST_ETHER
> +#define CONFIG_USB_ETHER_ASIX
> +#define CONFIG_USB_ETHER_MCS7830
> +#define CONFIG_USB_ETHER_SMSC95XX
> +#define CONFIG_MXC_USB_PORT 1
> +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
> +#define CONFIG_MXC_USB_FLAGS 0
> +
> +#define CONFIG_SYS_RTC_BUS_NUM 2
> +#define CONFIG_SYS_I2C_RTC_ADDR 0x30
> +
> +/* I2C Configs */
> +#define CONFIG_SYS_I2C
> +#define CONFIG_SYS_I2C_MXC
> +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
> +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
> +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
> +
> +/* PMIC Controller */
> +#define CONFIG_POWER
> +#define CONFIG_POWER_I2C
> +#define CONFIG_DIALOG_POWER
> +#define CONFIG_POWER_FSL
> +#define CONFIG_POWER_FSL_MC13892
> +#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
> +#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
> +
> +/* allow to overwrite serial and ethaddr */
> +#define CONFIG_ENV_OVERWRITE
> +#define CONFIG_CONS_INDEX 1
> +#define CONFIG_BAUDRATE 115200
> +
> +/* Command definition */
> +#define CONFIG_SUPPORT_RAW_INITRD
> +
> +#define CONFIG_ETHPRIME "FEC0"
> +
> +#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
> +#define CONFIG_SYS_TEXT_BASE 0x77800000
> +
> +#define PPD_CONFIG_NFS \
> + "nfsserver=192.168.252.95\0" \
> + "gatewayip=192.168.252.95\0" \
> + "netmask=255.255.255.0\0" \
> + "ipaddr=192.168.252.99\0" \
> + "kernsize=0x2000\0" \
> + "use_dhcp=0\0" \
> + "nfsroot=/opt/springdale/rd\0" \
> + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \
> + "${kern_ipconf} nfsroot=${nfsserver}:${nfsroot},v3,tcp rw\0" \
> + "choose_ip=if test $use_dhcp = 1; then set kern_ipconf ip=dhcp; " \
> + "set getcmd dhcp; else set kern_ipconf " \
> + "ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off; " \
> + "set getcmd tftp; fi\0" \
> + "nfs=run choose_ip setargs bootargs_nfs; ${getcmd} ${loadaddr} " \
> + "${nfsserver}:${image}; bootm ${loadaddr}\0" \
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + PPD_CONFIG_NFS \
> + "bootlimit=10\0" \
> + "image=/boot/fitImage\0" \
> + "fdt_high=0xffffffff\0" \
> + "dev=mmc\0" \
> + "devnum=0\0" \
> + "rootdev=mmcblk0p\0" \
> + "quiet=quiet loglevel=0\0" \
> + "console=" CONSOLE_DEV "\0" \
> + "lvds=ldb\0" \
> + "setargs=setenv bootargs ${lvds} jtag=on mem=2G " \
> + "vt.global_cursor_default=0 bootcause=${bootcause} ${quiet} " \
> + "console=${console} ${rtc_status}\0" \
> + "bootargs_emmc=setenv bootargs root=/dev/${rootdev}${partnum} ro " \
> + "rootwait ${bootargs}\0" \
> + "doquiet=if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \
> + "then setenv quiet; fi\0" \
> + "hasfirstboot=ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \
> + "/boot/bootcause/firstboot\0" \
> + "swappartitions=setexpr partnum 3 - ${partnum}\0" \
> + "failbootcmd=" \
> + "ppd_lcd_enable; " \
> + "msg=\"Monitor failed to start. " \
> + "Try again, or contact GE Service for support.\"; " \
> + "echo $msg; " \
> + "setenv stdout vga; " \
> + "echo \"\n\n\n\n \" $msg; " \
> + "setenv stdout serial; " \
> + "mw.b 0x7000A000 0xbc; " \
> + "mw.b 0x7000A001 0x00; " \
> + "ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \
> + "altbootcmd=" \
> + "run doquiet; " \
> + "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
> + "run hasfirstboot || setenv partnum 0; " \
> + "if test ${partnum} != 0; then " \
> + "setenv bootcause REVERT; " \
> + "run swappartitions loadimage doboot; " \
> + "fi; " \
> + "run failbootcmd\0" \
> + "loadimage=" \
> + "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
> + "doboot=" \
> + "echo Booting from ${dev}:${devnum}:${partnum} ...; " \
> + "run setargs; " \
> + "run bootargs_emmc; " \
> + "bootm ${loadaddr}\0" \
> + "tryboot=" \
> + "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
> + "run loadimage || run swappartitions && run loadimage || " \
> + "setenv partnum 0 && echo MISSING IMAGE;" \
> + "run doboot; " \
> + "run failbootcmd\0" \
> + "video-mode=" \
> + "lcd:800x480-24 at 60,monitor=lcd\0" \
> +
> +#define CONFIG_MMCBOOTCOMMAND \
> + "if mmc dev ${devnum}; then " \
> + "run doquiet; " \
> + "run tryboot; " \
> + "fi; " \
> +
> +#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
> +
> +#define CONFIG_ARP_TIMEOUT 200UL
> +
> +/* Miscellaneous configurable options */
> +#define CONFIG_SYS_LONGHELP /* undef to save memory */
> +#define CONFIG_AUTO_COMPLETE
> +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
> +
> +#define CONFIG_SYS_MAXARGS 48 /* max number of command args */
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
> +
> +#define CONFIG_SYS_MEMTEST_START 0x70000000
> +#define CONFIG_SYS_MEMTEST_END 0x70010000
> +
> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> +
> +#define CONFIG_CMDLINE_EDITING
> +
> +/* Physical Memory Map */
> +#define CONFIG_NR_DRAM_BANKS 2
> +#define PHYS_SDRAM_1 CSD0_BASE_ADDR
> +#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
> +#define PHYS_SDRAM_2 CSD1_BASE_ADDR
> +#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
> +#define PHYS_SDRAM_SIZE (gd->ram_size)
> +
> +#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
> +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
> +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +/* FLASH and environment organization */
> +#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
> +#define CONFIG_ENV_SIZE (8 * 1024)
> +#define CONFIG_ENV_IS_IN_MMC
> +#define CONFIG_SYS_MMC_ENV_DEV 0
> +
> +#define CONFIG_CMD_FUSE
> +#define CONFIG_FSL_IIM
> +
> +#define CONFIG_SYS_I2C_SPEED 100000
> +
> +/* I2C1 */
> +#define CONFIG_SYS_NUM_I2C_BUSES 9
> +#define CONFIG_SYS_I2C_MAX_HOPS 1
> +#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
> + {0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \
> + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
> + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
> + {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
> + {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
> + {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
> + {0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \
> + {0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \
> + }
> +
> +#define CONFIG_BCH
> +
> +#define CONFIG_BOOTCOUNT_LIMIT
> +
> +/* Backlight Control */
> +#define CONFIG_PWM_IMX
> +#define CONFIG_IMX6_PWM_PER_CLK 66666000
> +
> +/* Framebuffer and LCD */
> +#ifdef CONFIG_VIDEO
> + #define CONFIG_VIDEO_IPUV3
> +#endif
> +
> +#endif /* __CONFIG_H */
>
Acked-by: Stefano Babic <sbabic at denx.de>
Best regards,
Stefano
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
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