[U-Boot] [PATCH] clk: clk_stm32f7: fix PLL clock division factor

[Simon Glass]

On 26 October 2017 at 05:23,  <patrice.chotard at st.com> wrote:
> From: Patrice Chotard <patrice.chotard at st.com>
>
> Fix clock division factor initialization for RCC_PLLCFGR
> registers.
>
> PLLR bits (bit 31-28) in RCC_PLLCFGR must not be cleared,
> it's a forbidden value. So update RCC_PLLCFGR using
> clrsetbits_le32() to set only necessary bits fields.
>
> Signed-off-by: Patrice Chotard <patrice.chotard at st.com>
> ---
>  drivers/clk/clk_stm32f7.c | 16 +++++++++-------
>  1 file changed, 9 insertions(+), 7 deletions(-)

Reviewed-by: Simon Glass <sjg at chromium.org>