[U-Boot] [PATCH 02/11] clk: stm32f7: retrieve PWR base address from DT
patrice.chotard at st.com
patrice.chotard at st.com
Wed Nov 15 12:14:44 UTC 2017
From: Patrice Chotard <patrice.chotard at st.com>
PWR IP is used to enable over-drive feature in
order to reach a higher frequency.
Get its base address from DT instead of hard-coded value
Signed-off-by: Patrice Chotard <patrice.chotard at st.com>
Reviewed-by: Vikas Manocha <vikas.manocha at st.com>
---
arch/arm/include/asm/arch-stm32f4/stm32_pwr.h | 23 +++++++++++++++++++
arch/arm/include/asm/arch-stm32f7/stm32.h | 7 ------
arch/arm/include/asm/arch-stm32f7/stm32_pwr.h | 25 +++++++++++++++++++++
drivers/clk/clk_stm32f7.c | 32 ++++++++++++++++++---------
4 files changed, 69 insertions(+), 18 deletions(-)
create mode 100644 arch/arm/include/asm/arch-stm32f4/stm32_pwr.h
create mode 100644 arch/arm/include/asm/arch-stm32f7/stm32_pwr.h
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h b/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h
new file mode 100644
index 0000000..bfe5469
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard at st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __STM32_PWR_H_
+
+/*
+ * Offsets of some PWR registers
+ */
+#define PWR_CR1_ODEN BIT(16)
+#define PWR_CR1_ODSWEN BIT(17)
+#define PWR_CSR1_ODRDY BIT(16)
+#define PWR_CSR1_ODSWRDY BIT(17)
+
+struct stm32_pwr_regs {
+ u32 cr1; /* power control register 1 */
+ u32 csr1; /* power control/status register 2 */
+};
+
+#endif /* __STM32_PWR_H_ */
diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h
index d6412a0..0117039 100644
--- a/arch/arm/include/asm/arch-stm32f7/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f7/stm32.h
@@ -95,13 +95,6 @@ struct stm32_rcc_regs {
};
#define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE)
-struct stm32_pwr_regs {
- u32 cr1; /* power control register 1 */
- u32 csr1; /* power control/status register 2 */
- u32 cr2; /* power control register 2 */
- u32 csr2; /* power control/status register 2 */
-};
-#define STM32_PWR ((struct stm32_pwr_regs *)PWR_BASE)
void stm32_flash_latency_cfg(int latency);
diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h b/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h
new file mode 100644
index 0000000..917dd46
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard at st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __STM32_PWR_H_
+
+/*
+ * Offsets of some PWR registers
+ */
+#define PWR_CR1_ODEN BIT(16)
+#define PWR_CR1_ODSWEN BIT(17)
+#define PWR_CSR1_ODRDY BIT(16)
+#define PWR_CSR1_ODSWRDY BIT(17)
+
+struct stm32_pwr_regs {
+ u32 cr1; /* power control register 1 */
+ u32 csr1; /* power control/status register 2 */
+ u32 cr2; /* power control register 2 */
+ u32 csr2; /* power control/status register 2 */
+};
+
+#endif /* __STM32_PWR_H_ */
diff --git a/drivers/clk/clk_stm32f7.c b/drivers/clk/clk_stm32f7.c
index f1a9e9c..0fa838c 100644
--- a/drivers/clk/clk_stm32f7.c
+++ b/drivers/clk/clk_stm32f7.c
@@ -8,10 +8,12 @@
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
+
#include <asm/io.h>
#include <asm/arch/rcc.h>
#include <asm/arch/stm32.h>
#include <asm/arch/stm32_periph.h>
+#include <asm/arch/stm32_pwr.h>
#include <dt-bindings/mfd/stm32f7-rcc.h>
@@ -52,13 +54,6 @@
#define RCC_CFGR_PPRE1_SHIFT 10
#define RCC_CFGR_PPRE2_SHIFT 13
-/*
- * Offsets of some PWR registers
- */
-#define PWR_CR1_ODEN BIT(16)
-#define PWR_CR1_ODSWEN BIT(17)
-#define PWR_CSR1_ODRDY BIT(16)
-#define PWR_CSR1_ODSWRDY BIT(17)
struct pll_psc {
u8 pll_m;
@@ -88,6 +83,7 @@ struct pll_psc {
struct stm32_clk {
struct stm32_rcc_regs *base;
+ struct stm32_pwr_regs *pwr_regs;
};
#if !defined(CONFIG_STM32_HSE_HZ)
@@ -115,6 +111,7 @@ static int configure_clocks(struct udevice *dev)
{
struct stm32_clk *priv = dev_get_priv(dev);
struct stm32_rcc_regs *regs = priv->base;
+ struct stm32_pwr_regs *pwr = priv->pwr_regs;
/* Reset RCC configuration */
setbits_le32(®s->cr, RCC_CR_HSION);
@@ -153,14 +150,14 @@ static int configure_clocks(struct udevice *dev)
/* Enable high performance mode, System frequency up to 200 MHz */
setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN);
- setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN);
+ setbits_le32(&pwr->cr1, PWR_CR1_ODEN);
/* Infinite wait! */
- while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODRDY))
+ while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY))
;
/* Enable the Over-drive switch */
- setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODSWEN);
+ setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN);
/* Infinite wait! */
- while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODSWRDY))
+ while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY))
;
stm32_flash_latency_cfg(5);
@@ -268,6 +265,9 @@ void clock_setup(int peripheral)
static int stm32_clk_probe(struct udevice *dev)
{
+ struct ofnode_phandle_args args;
+ int err;
+
debug("%s: stm32_clk_probe\n", __func__);
struct stm32_clk *priv = dev_get_priv(dev);
@@ -279,6 +279,16 @@ static int stm32_clk_probe(struct udevice *dev)
priv->base = (struct stm32_rcc_regs *)addr;
+ err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
+ &args);
+ if (err) {
+ debug("%s: can't find syscon device (%d)\n", __func__,
+ err);
+ return err;
+ }
+
+ priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node);
+
configure_clocks(dev);
return 0;
--
1.9.1
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