[U-Boot] [PATCH 8/9] fsl: csu: enable ns access for PFE

[Poonam Aggrwal]

Hello Calvin,
Minor comments below.

Regards
Poonam

> -----Original Message-----
> From: U-Boot [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Calvin
> Johnson
> Sent: Monday, October 09, 2017 2:42 PM
> To: u-boot at lists.denx.de
> Cc: joe.hershberger at ni.com; Anji Jagarlmudi <anji.jagarlmudi at nxp.com>
> Subject: [U-Boot] [PATCH 8/9] fsl: csu: enable ns access for PFE
Can be reworded.
nxp: arch/fsl-layerscape:
> 
> Enable non-secure access for PFE block.
may want to reword:
Enable accesses to PFE registers for Non Secure masters by CSU programming
> 
> Signed-off-by: Calvin Johnson <calvin.johnson at nxp.com>
> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi at nxp.com>
> ---
>  arch/arm/include/asm/arch-fsl-layerscape/ns_access.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
> b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
> index f46f1d8..fe97a93 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
> @@ -26,6 +26,7 @@ enum csu_cslx_ind {
>  	CSU_CSLX_PCIE3_IO,
>  	CSU_CSLX_USB3 = 20,
>  	CSU_CSLX_USB2,
> +	CSU_CSLX_PFE = 23,
>  	CSU_CSLX_SERDES = 32,
>  	CSU_CSLX_QDMA,
>  	CSU_CSLX_LPUART2,
> @@ -105,6 +106,7 @@ static struct csu_ns_dev ns_dev[] = {
>  	 {CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
>  	 {CSU_CSLX_USB3, CSU_ALL_RW},
>  	 {CSU_CSLX_USB2, CSU_ALL_RW},
> +	 {CSU_CSLX_PFE, CSU_ALL_RW},
>  	 {CSU_CSLX_SERDES, CSU_ALL_RW},
>  	 {CSU_CSLX_QDMA, CSU_ALL_RW},
>  	 {CSU_CSLX_LPUART2, CSU_ALL_RW},
> --
> 2.7.4
> 
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