[U-Boot] [PATCH v2 1/3] rockchip: rk3036: fix pll config for correct frequency

[Kever Yang]

There is a fixed div-2 between PLL and clk_ddr/clk_ddrphy,
so we need to double to pll output and then ddr can work
in correct frequency.

Signed-off-by: Kever Yang <kever.yang at rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich at theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich at theobroma-systems.com>
---

Changes in v2:
- update comment for code change

 arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
index 460dd60..1d3fc1a 100644
--- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
@@ -34,10 +34,11 @@ struct rk3036_sdram_priv {
 	struct rk3036_ddr_config ddr_config;
 };
 
-/* use integer mode, 396MHz dpll setting
+/*
+ * use integer mode, dpll output 792MHz and ddr get 396MHz
  * refdiv, fbdiv, postdiv1, postdiv2
  */
-const struct pll_div dpll_init_cfg = {1, 50, 3, 1};
+const struct pll_div dpll_init_cfg = {1, 66, 2, 1};
 
 /* 396Mhz ddr timing */
 const struct rk3036_ddr_timing ddr_timing = {0x18c,
-- 
1.9.1