[U-Boot] [PATCH] clk: clk_stm32f7: fix PLL clock division factor
patrice.chotard at st.com
patrice.chotard at st.com
Thu Oct 26 11:23:19 UTC 2017
From: Patrice Chotard <patrice.chotard at st.com>
Fix clock division factor initialization for RCC_PLLCFGR
registers.
PLLR bits (bit 31-28) in RCC_PLLCFGR must not be cleared,
it's a forbidden value. So update RCC_PLLCFGR using
clrsetbits_le32() to set only necessary bits fields.
Signed-off-by: Patrice Chotard <patrice.chotard at st.com>
---
drivers/clk/clk_stm32f7.c | 16 +++++++++-------
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/clk_stm32f7.c b/drivers/clk/clk_stm32f7.c
index 96a06b8..4b0e449 100644
--- a/drivers/clk/clk_stm32f7.c
+++ b/drivers/clk/clk_stm32f7.c
@@ -135,13 +135,15 @@ static int configure_clocks(struct udevice *dev)
| (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
/* Configure the main PLL */
- uint32_t pllcfgr = 0;
- pllcfgr = RCC_PLLCFGR_PLLSRC; /* pll source HSE */
- pllcfgr |= sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT;
- pllcfgr |= sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT;
- pllcfgr |= ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT;
- pllcfgr |= sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT;
- writel(pllcfgr, ®s->pllcfgr);
+ setbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */
+ clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLM_MASK,
+ sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT);
+ clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLN_MASK,
+ sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT);
+ clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLP_MASK,
+ ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT);
+ clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
+ sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
/* Enable the main PLL */
setbits_le32(®s->cr, RCC_CR_PLLON);
--
1.9.1
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