[U-Boot] [U-Boot,2/3] imx: mx6: correct IPU clock

Eric Nelson eric at nelint.com
Tue Sep 5 13:41:42 UTC 2017


Hi Stefano,

On 09/05/2017 06:30 AM, Stefano Babic wrote:
> On 05/09/2017 14:56, Fabio Estevam wrote:
>> Hi Eric,
>>
>> On Mon, Sep 4, 2017 at 11:37 PM, Eric Nelson <ericnelsonaz at gmail.com> wrote:
>>
>>>> --- a/include/configs/mx6sabre_common.h
>>>> +++ b/include/configs/mx6sabre_common.h
>>>> @@ -225,7 +225,11 @@
>>>>    #define CONFIG_BMP_16BPP
>>>>    #define CONFIG_VIDEO_LOGO
>>>>    #define CONFIG_VIDEO_BMP_LOGO
>>>> -#define CONFIG_IPUV3_CLK 260000000
>>>> +#ifdef CONFIG_MX6DL
>>>> +#define CONFIG_IPUV3_CLK 198000000
>>>> +#else
>>>> +#define CONFIG_IPUV3_CLK 264000000
>>>> +#endif
>>>
>>>
>>>
>>> Note that this should probably be applied for other boards
>>> which are compiled for multiple CPU types.
>>>
>>> At least the Boundary Nitrogen boards, but probably others
>>> like Wand have ordering options for DL or Solo processors
>>> and may need the reduced clock rate.
>>
>> Agreed. The clock frequency decision should be done in run-time rather
>> than in build-time.
> 
> I agree, too. We have mechanism to take decisions at run time, at least
> based on SOC type. Anyway, Anatolji has already merged this - should be
> better to revert it ?
> 

I don't think it should be reverted until we have a run-time decision
in place, or we'll re-introduce whatever problem the higher rate
caused, at least on SABRE boards with Solo or Dual-Lite processors.

I'm still wondering whether Peng has a description of the ramifications
of the higher rate on DL/Solo processors.

Regards,


Eric


More information about the U-Boot mailing list