[U-Boot] [U-Boot, 1/2] clk: at91: utmi: Set the reference clock frequency

[Tom Rini]

On Tue, Sep 05, 2017 at 06:30:07PM +0800, Wenyou Yang wrote:
> By default, it is assumed that the UTMI clock is generated from
> a 12 MHz reference clock (MAINCK). If it's not the case, the FREQ
> field of the SFR_UTMICKTRIM has to be updated to generate the UTMI
> clock in the proper way.
> 
> The UTMI clock has a fixed rate of 480 MHz. In fact, there is no
> multiplier we can configure. The multiplier is managed internally,
> depending on the reference clock frequency, to achieve the target
> of 480 MHz.
> 
> The patch is cloned from the patch of mailing-list:
> 	[PATCH v2] clk: at91: utmi: set the mainck rate
> 
> Signed-off-by: Wenyou Yang <wenyou.yang at microchip.com>
> ---
> 
>  arch/arm/mach-at91/include/mach/sama5_sfr.h |  5 ++
>  drivers/clk/at91/Kconfig                    |  4 ++
>  drivers/clk/at91/clk-utmi.c                 | 77 ++++++++++++++++++++++++++++-
>  drivers/clk/at91/pmc.h                      |  3 ++
>  4 files changed, 87 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/include/mach/sama5_sfr.h b/arch/arm/mach-at91/include/mach/sama5_sfr.h
> index b805a2c934..965631aad7 100644
> --- a/arch/arm/mach-at91/include/mach/sama5_sfr.h
> +++ b/arch/arm/mach-at91/include/mach/sama5_sfr.h
> @@ -28,6 +28,9 @@ struct atmel_sfr {
>  	u32 l2cc_hramc;	/* 0x58 */
>  };
>  
> +/* Register Mapping*/
> +#define AT91_SFR_UTMICKTRIM	0x30	/* UTMI Clock Trimming Register */
> +
>  /* Bit field in DDRCFG */
>  #define ATMEL_SFR_DDRCFG_FDQIEN		0x00010000
>  #define ATMEL_SFR_DDRCFG_FDQSIEN	0x00020000
> @@ -56,6 +59,8 @@ struct atmel_sfr {
>  #define AT91_SFR_EBICFG_SCH1_OFF		(0x0 << 12)
>  #define AT91_SFR_EBICFG_SCH1_ON			(0x1 << 12)
>  
> +#define AT91_UTMICKTRIM_FREQ		GENMASK(1, 0)
> +
>  /* Bit field in AICREDIR */
>  #define ATMEL_SFR_AICREDIR_NSAIC	0x00000001
>  
> diff --git a/drivers/clk/at91/Kconfig b/drivers/clk/at91/Kconfig
> index 904ed48e51..2f112afa31 100644
> --- a/drivers/clk/at91/Kconfig
> +++ b/drivers/clk/at91/Kconfig
> @@ -15,6 +15,10 @@ config CLK_AT91
>  config AT91_UTMI
>  	bool "Support UTMI PLL Clock"
>  	depends on CLK_AT91
> +	select REGMAP
> +	select SPL_REGMAP
> +	select SYSCON
> +	select SPL_SYSCON
>  	help

Does this depend on other series in particular?  Not all boards that set
AT91_UTMI also have SPL_DM enabled, which is required for SPL_REGMAP,
thanks!

-- 
Tom
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