[U-Boot] [PATCH v5 1/3] armv8:fsl-layerscape: Consolidate registers space defination for CCI-400 bus

[York Sun]

On 08/10/2017 10:39 PM, Ashish Kumar wrote:
> CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
> provides full cache coherency between two clusters of multi-core
> CPUs and I/O coherency for devices and I/O masters.
> 
> This patch add new CONFIG defination "SYS_FSL_HAS_CCI400" and
> moves existing register space definaton of CCI-400 bus
> from immap_lsch2 to fsl_immap, so that it can be used
> for both chasis 2 and chasis 3.
> 
> "CONFIG_SYS_CCI400_ADDR" is depricated and new SYS_CCI400_OFFSET
> is introduced in Kconfig
> 
> Signed-off-by: Ashish Kumar <Ashish.Kumar at nxp.com>
> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
> ---
> v3:
>   This is v3 for https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.ozlabs.org%2Fpatch%2F731464%2F&data=01%7C01%7Cyork.sun%40nxp.com%7C4f61d387ca34498ea03508d4e07b6201%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0&sdata=%2Bws6L80BORcRZtZd6O6Maun425cZ7bfUhGik1eJaO1I%3D&reserved=0
> v4:
>   Header file included in middle of the file in cpu.c
> v5:
>   Moving ls1021aqds to 2/3-armv7 of this patch-set
> 

Squashed three patches into one commit. Applied to fsl-qoriq master. Thanks.

York