[U-Boot] [PATCH v2 14/14] sunxi: sina33: Sync the device tree with the kernel

Łukasz Majewski lukma at denx.de
Wed Sep 13 10:52:09 UTC 2017


On 09/12/2017 09:01 PM, Maxime Ripard wrote:
> The kernel DT of the SinA33 has evolved quite a bit. Make sure we sync it
> and its upstream DTSI to be able to use the OTG. The DTs were taken from
> the 4.13 kernel release.
> 
> Reviewed-by: Simon Glass <sjg at chromium.org>
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> ---
>   arch/arm/dts/axp223.dtsi                      |  58 ++-
>   arch/arm/dts/axp22x.dtsi                      |  10 +-
>   arch/arm/dts/sun8i-a23-a33.dtsi               | 446 +++++++-----------
>   arch/arm/dts/sun8i-a33-sinlinx-sina33.dts     |  43 ++-
>   arch/arm/dts/sun8i-a33.dtsi                   | 477 +++++++++++++++----
>   include/dt-bindings/clock/sun8i-a23-a33-ccu.h | 127 +++++-
>   include/dt-bindings/reset/sun8i-a23-a33-ccu.h |  87 +++-
>   7 files changed, 914 insertions(+), 334 deletions(-)
>   create mode 100644 arch/arm/dts/axp223.dtsi
>   create mode 100644 include/dt-bindings/clock/sun8i-a23-a33-ccu.h
>   create mode 100644 include/dt-bindings/reset/sun8i-a23-a33-ccu.h
> 
> diff --git a/arch/arm/dts/axp223.dtsi b/arch/arm/dts/axp223.dtsi
> new file mode 100644
> index 000000000000..b91b6c1278c7
> --- /dev/null
> +++ b/arch/arm/dts/axp223.dtsi
> @@ -0,0 +1,58 @@
> +/*
> + * Copyright 2016 Free Electrons
> + *
> + * Quentin Schulz <quentin.schulz at free-electrons.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This file is distributed in the hope that it will be useful,
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use,
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/*
> + * AXP223 Integrated Power Management Chip
> + * http://www.x-powers.com/product/AXP22X.php
> + * http://dl.linux-sunxi.org/AXP/AXP223-en.pdf
> + *
> + * The AXP223 shares most of its logic with the AXP221 but it has some
> + * differences, for the VBUS driver for example.
> + */
> +
> +#include "axp22x.dtsi"
> +
> +&usb_power_supply {
> +	compatible = "x-powers,axp223-usb-power-supply";
> +};
> diff --git a/arch/arm/dts/axp22x.dtsi b/arch/arm/dts/axp22x.dtsi
> index 458b6681e3ec..87fb08e812ec 100644
> --- a/arch/arm/dts/axp22x.dtsi
> +++ b/arch/arm/dts/axp22x.dtsi
> @@ -52,6 +52,16 @@
>   	interrupt-controller;
>   	#interrupt-cells = <1>;
>   
> +	ac_power_supply: ac-power-supply {
> +		compatible = "x-powers,axp221-ac-power-supply";
> +		status = "disabled";
> +	};
> +
> +	battery_power_supply: battery-power-supply {
> +		compatible = "x-powers,axp221-battery-power-supply";
> +		status = "disabled";
> +	};
> +
>   	regulators {
>   		/* Default work frequency for buck regulators */
>   		x-powers,dcdc-freq = <3000>;
> diff --git a/arch/arm/dts/sun8i-a23-a33.dtsi b/arch/arm/dts/sun8i-a23-a33.dtsi
> index f97c38f097d1..ea50dda75adc 100644
> --- a/arch/arm/dts/sun8i-a23-a33.dtsi
> +++ b/arch/arm/dts/sun8i-a23-a33.dtsi
> @@ -46,7 +46,8 @@
>   
>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>   
> -#include <dt-bindings/pinctrl/sun4i-a10.h>
> +#include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
> +#include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
>   
>   / {
>   	interrupt-parent = <&gic>;
> @@ -60,7 +61,9 @@
>   			compatible = "allwinner,simple-framebuffer",
>   				     "simple-framebuffer";
>   			allwinner,pipeline = "de_be0-lcd0";
> -			clocks = <&pll6 0>;
> +			clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
> +				 <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
> +				 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
>   			status = "disabled";
>   		};
>   	};
> @@ -80,7 +83,7 @@
>   		#address-cells = <1>;
>   		#size-cells = <0>;
>   
> -		cpu at 0 {
> +		cpu0: cpu at 0 {
>   			compatible = "arm,cortex-a7";
>   			device_type = "cpu";
>   			reg = <0>;
> @@ -102,151 +105,16 @@
>   			#clock-cells = <0>;
>   			compatible = "fixed-clock";
>   			clock-frequency = <24000000>;
> +			clock-accuracy = <50000>;
>   			clock-output-names = "osc24M";
>   		};
>   
> -		osc32k: osc32k_clk {
> +		ext_osc32k: ext_osc32k_clk {
>   			#clock-cells = <0>;
>   			compatible = "fixed-clock";
>   			clock-frequency = <32768>;
> -			clock-output-names = "osc32k";
> -		};
> -
> -		pll1: clk at 01c20000 {
> -			#clock-cells = <0>;
> -			compatible = "allwinner,sun8i-a23-pll1-clk";
> -			reg = <0x01c20000 0x4>;
> -			clocks = <&osc24M>;
> -			clock-output-names = "pll1";
> -		};
> -
> -		/* dummy clock until actually implemented */
> -		pll5: pll5_clk {
> -			#clock-cells = <0>;
> -			compatible = "fixed-clock";
> -			clock-frequency = <0>;
> -			clock-output-names = "pll5";
> -		};
> -
> -		pll6: clk at 01c20028 {
> -			#clock-cells = <1>;
> -			compatible = "allwinner,sun6i-a31-pll6-clk";
> -			reg = <0x01c20028 0x4>;
> -			clocks = <&osc24M>;
> -			clock-output-names = "pll6", "pll6x2";
> -		};
> -
> -		cpu: cpu_clk at 01c20050 {
> -			#clock-cells = <0>;
> -			compatible = "allwinner,sun4i-a10-cpu-clk";
> -			reg = <0x01c20050 0x4>;
> -
> -			/*
> -			 * PLL1 is listed twice here.
> -			 * While it looks suspicious, it's actually documented
> -			 * that way both in the datasheet and in the code from
> -			 * Allwinner.
> -			 */
> -			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
> -			clock-output-names = "cpu";
> -		};
> -
> -		axi: axi_clk at 01c20050 {
> -			#clock-cells = <0>;
> -			compatible = "allwinner,sun8i-a23-axi-clk";
> -			reg = <0x01c20050 0x4>;
> -			clocks = <&cpu>;
> -			clock-output-names = "axi";
> -		};
> -
> -		ahb1: ahb1_clk at 01c20054 {
> -			#clock-cells = <0>;
> -			compatible = "allwinner,sun6i-a31-ahb1-clk";
> -			reg = <0x01c20054 0x4>;
> -			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
> -			clock-output-names = "ahb1";
> -		};
> -
> -		apb1: apb1_clk at 01c20054 {
> -			#clock-cells = <0>;
> -			compatible = "allwinner,sun4i-a10-apb0-clk";
> -			reg = <0x01c20054 0x4>;
> -			clocks = <&ahb1>;
> -			clock-output-names = "apb1";
> -		};
> -
> -		apb1_gates: clk at 01c20068 {
> -			#clock-cells = <1>;
> -			compatible = "allwinner,sun8i-a23-apb1-gates-clk";
> -			reg = <0x01c20068 0x4>;
> -			clocks = <&apb1>;
> -			clock-indices = <0>, <5>,
> -					<12>, <13>;
> -			clock-output-names = "apb1_codec", "apb1_pio",
> -					"apb1_daudio0",	"apb1_daudio1";
> -		};
> -
> -		apb2: clk at 01c20058 {
> -			#clock-cells = <0>;
> -			compatible = "allwinner,sun4i-a10-apb1-clk";
> -			reg = <0x01c20058 0x4>;
> -			clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
> -			clock-output-names = "apb2";
> -		};
> -
> -		apb2_gates: clk at 01c2006c {
> -			#clock-cells = <1>;
> -			compatible = "allwinner,sun8i-a23-apb2-gates-clk";
> -			reg = <0x01c2006c 0x4>;
> -			clocks = <&apb2>;
> -			clock-indices = <0>, <1>,
> -					<2>, <16>,
> -					<17>, <18>,
> -					<19>, <20>;
> -			clock-output-names = "apb2_i2c0", "apb2_i2c1",
> -					"apb2_i2c2", "apb2_uart0",
> -					"apb2_uart1", "apb2_uart2",
> -					"apb2_uart3", "apb2_uart4";
> -		};
> -
> -		mmc0_clk: clk at 01c20088 {
> -			#clock-cells = <1>;
> -			compatible = "allwinner,sun4i-a10-mmc-clk";
> -			reg = <0x01c20088 0x4>;
> -			clocks = <&osc24M>, <&pll6 0>;
> -			clock-output-names = "mmc0",
> -					     "mmc0_output",
> -					     "mmc0_sample";
> -		};
> -
> -		mmc1_clk: clk at 01c2008c {
> -			#clock-cells = <1>;
> -			compatible = "allwinner,sun4i-a10-mmc-clk";
> -			reg = <0x01c2008c 0x4>;
> -			clocks = <&osc24M>, <&pll6 0>;
> -			clock-output-names = "mmc1",
> -					     "mmc1_output",
> -					     "mmc1_sample";
> -		};
> -
> -		mmc2_clk: clk at 01c20090 {
> -			#clock-cells = <1>;
> -			compatible = "allwinner,sun4i-a10-mmc-clk";
> -			reg = <0x01c20090 0x4>;
> -			clocks = <&osc24M>, <&pll6 0>;
> -			clock-output-names = "mmc2",
> -					     "mmc2_output",
> -					     "mmc2_sample";
> -		};
> -
> -		usb_clk: clk at 01c200cc {
> -			#clock-cells = <1>;
> -			#reset-cells = <1>;
> -			compatible = "allwinner,sun8i-a23-usb-clk";
> -			reg = <0x01c200cc 0x4>;
> -			clocks = <&osc24M>;
> -			clock-output-names = "usb_phy0", "usb_phy1", "usb_hsic",
> -					     "usb_hsic_12M", "usb_ohci0";
> +			clock-accuracy = <50000>;
> +			clock-output-names = "ext-osc32k";
>   		};
>   	};
>   
> @@ -260,24 +128,23 @@
>   			compatible = "allwinner,sun8i-a23-dma";
>   			reg = <0x01c02000 0x1000>;
>   			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&ahb1_gates 6>;
> -			resets = <&ahb1_rst 6>;
> +			clocks = <&ccu CLK_BUS_DMA>;
> +			resets = <&ccu RST_BUS_DMA>;
>   			#dma-cells = <1>;
>   		};
>   
>   		mmc0: mmc at 01c0f000 {
> -			compatible = "allwinner,sun7i-a20-mmc",
> -				     "allwinner,sun5i-a13-mmc";
> +			compatible = "allwinner,sun7i-a20-mmc";
>   			reg = <0x01c0f000 0x1000>;
> -			clocks = <&ahb1_gates 8>,
> -				 <&mmc0_clk 0>,
> -				 <&mmc0_clk 1>,
> -				 <&mmc0_clk 2>;
> +			clocks = <&ccu CLK_BUS_MMC0>,
> +				 <&ccu CLK_MMC0>,
> +				 <&ccu CLK_MMC0_OUTPUT>,
> +				 <&ccu CLK_MMC0_SAMPLE>;
>   			clock-names = "ahb",
>   				      "mmc",
>   				      "output",
>   				      "sample";
> -			resets = <&ahb1_rst 8>;
> +			resets = <&ccu RST_BUS_MMC0>;
>   			reset-names = "ahb";
>   			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
>   			status = "disabled";
> @@ -286,18 +153,17 @@
>   		};
>   
>   		mmc1: mmc at 01c10000 {
> -			compatible = "allwinner,sun7i-a20-mmc",
> -				     "allwinner,sun5i-a13-mmc";
> +			compatible = "allwinner,sun7i-a20-mmc";
>   			reg = <0x01c10000 0x1000>;
> -			clocks = <&ahb1_gates 9>,
> -				 <&mmc1_clk 0>,
> -				 <&mmc1_clk 1>,
> -				 <&mmc1_clk 2>;
> +			clocks = <&ccu CLK_BUS_MMC1>,
> +				 <&ccu CLK_MMC1>,
> +				 <&ccu CLK_MMC1_OUTPUT>,
> +				 <&ccu CLK_MMC1_SAMPLE>;
>   			clock-names = "ahb",
>   				      "mmc",
>   				      "output",
>   				      "sample";
> -			resets = <&ahb1_rst 9>;
> +			resets = <&ccu RST_BUS_MMC1>;
>   			reset-names = "ahb";
>   			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
>   			status = "disabled";
> @@ -306,18 +172,17 @@
>   		};
>   
>   		mmc2: mmc at 01c11000 {
> -			compatible = "allwinner,sun7i-a20-mmc",
> -				     "allwinner,sun5i-a13-mmc";
> +			compatible = "allwinner,sun7i-a20-mmc";
>   			reg = <0x01c11000 0x1000>;
> -			clocks = <&ahb1_gates 10>,
> -				 <&mmc2_clk 0>,
> -				 <&mmc2_clk 1>,
> -				 <&mmc2_clk 2>;
> +			clocks = <&ccu CLK_BUS_MMC2>,
> +				 <&ccu CLK_MMC2>,
> +				 <&ccu CLK_MMC2_OUTPUT>,
> +				 <&ccu CLK_MMC2_SAMPLE>;
>   			clock-names = "ahb",
>   				      "mmc",
>   				      "output",
>   				      "sample";
> -			resets = <&ahb1_rst 10>;
> +			resets = <&ccu RST_BUS_MMC2>;
>   			reset-names = "ahb";
>   			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
>   			status = "disabled";
> @@ -325,12 +190,55 @@
>   			#size-cells = <0>;
>   		};
>   
> +		nfc: nand at 01c03000 {
> +			compatible = "allwinner,sun4i-a10-nand";
> +			reg = <0x01c03000 0x1000>;
> +			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
> +			clock-names = "ahb", "mod";
> +			resets = <&ccu RST_BUS_NAND>;
> +			reset-names = "ahb";
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		usb_otg: usb at 01c19000 {
> +			/* compatible gets set in SoC specific dtsi file */
> +			reg = <0x01c19000 0x0400>;
> +			clocks = <&ccu CLK_BUS_OTG>;
> +			resets = <&ccu RST_BUS_OTG>;
> +			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "mc";
> +			phys = <&usbphy 0>;
> +			phy-names = "usb";
> +			extcon = <&usbphy 0>;
> +			status = "disabled";
> +		};
> +
> +		usbphy: phy at 01c19400 {
> +			/*
> +			 * compatible and address regions get set in
> +			 * SoC specific dtsi file
> +			 */
> +			clocks = <&ccu CLK_USB_PHY0>,
> +				 <&ccu CLK_USB_PHY1>;
> +			clock-names = "usb0_phy",
> +				      "usb1_phy";
> +			resets = <&ccu RST_USB_PHY0>,
> +				 <&ccu RST_USB_PHY1>;
> +			reset-names = "usb0_reset",
> +				      "usb1_reset";
> +			status = "disabled";
> +			#phy-cells = <1>;
> +		};
> +
>   		ehci0: usb at 01c1a000 {
>   			compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
>   			reg = <0x01c1a000 0x100>;
>   			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&ahb1_gates 26>;
> -			resets = <&ahb1_rst 26>;
> +			clocks = <&ccu CLK_BUS_EHCI>;
> +			resets = <&ccu RST_BUS_EHCI>;
>   			phys = <&usbphy 1>;
>   			phy-names = "usb";
>   			status = "disabled";
> @@ -340,101 +248,100 @@
>   			compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
>   			reg = <0x01c1a400 0x100>;
>   			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&ahb1_gates 29>, <&usb_clk 16>;
> -			resets = <&ahb1_rst 29>;
> +			clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;
> +			resets = <&ccu RST_BUS_OHCI>;
>   			phys = <&usbphy 1>;
>   			phy-names = "usb";
>   			status = "disabled";
>   		};
>   
> +		ccu: clock at 01c20000 {
> +			reg = <0x01c20000 0x400>;
> +			clocks = <&osc24M>, <&rtc 0>;
> +			clock-names = "hosc", "losc";
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +		};
> +
>   		pio: pinctrl at 01c20800 {
>   			/* compatible gets set in SoC specific dtsi file */
>   			reg = <0x01c20800 0x400>;
>   			/* interrupts get set in SoC specific dtsi file */
> -			clocks = <&apb1_gates 5>;
> +			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
> +			clock-names = "apb", "hosc", "losc";
>   			gpio-controller;
>   			interrupt-controller;
>   			#interrupt-cells = <3>;
>   			#gpio-cells = <3>;
>   
>   			uart0_pins_a: uart0 at 0 {
> -				allwinner,pins = "PF2", "PF4";
> -				allwinner,function = "uart0";
> -				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> -				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +				pins = "PF2", "PF4";
> +				function = "uart0";
> +			};
> +
> +			uart1_pins_a: uart1 at 0 {
> +				pins = "PG6", "PG7";
> +				function = "uart1";
> +			};
> +
> +			uart1_pins_cts_rts_a: uart1-cts-rts at 0 {
> +				pins = "PG8", "PG9";
> +				function = "uart1";
>   			};
>   
>   			mmc0_pins_a: mmc0 at 0 {
> -				allwinner,pins = "PF0", "PF1", "PF2",
> -						 "PF3", "PF4", "PF5";
> -				allwinner,function = "mmc0";
> -				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> -				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +				pins = "PF0", "PF1", "PF2",
> +				       "PF3", "PF4", "PF5";
> +				function = "mmc0";
> +				drive-strength = <30>;
> +				bias-pull-up;
>   			};
>   
>   			mmc1_pins_a: mmc1 at 0 {
> -				allwinner,pins = "PG0", "PG1", "PG2",
> -						 "PG3", "PG4", "PG5";
> -				allwinner,function = "mmc1";
> -				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> -				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +				pins = "PG0", "PG1", "PG2",
> +				       "PG3", "PG4", "PG5";
> +				function = "mmc1";
> +				drive-strength = <30>;
> +				bias-pull-up;
>   			};
>   
>   			mmc2_8bit_pins: mmc2_8bit {
> -				allwinner,pins = "PC5", "PC6", "PC8",
> -						 "PC9", "PC10", "PC11",
> -						 "PC12", "PC13", "PC14",
> -						 "PC15", "PC16";
> -				allwinner,function = "mmc2";
> -				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> -				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +				pins = "PC5", "PC6", "PC8",
> +				       "PC9", "PC10", "PC11",
> +				       "PC12", "PC13", "PC14",
> +				       "PC15", "PC16";
> +				function = "mmc2";
> +				drive-strength = <30>;
> +				bias-pull-up;
>   			};
>   
>   			pwm0_pins: pwm0 {
> -				allwinner,pins = "PH0";
> -				allwinner,function = "pwm0";
> -				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> -				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +				pins = "PH0";
> +				function = "pwm0";
>   			};
>   
>   			i2c0_pins_a: i2c0 at 0 {
> -				allwinner,pins = "PH2", "PH3";
> -				allwinner,function = "i2c0";
> -				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> -				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +				pins = "PH2", "PH3";
> +				function = "i2c0";
>   			};
>   
>   			i2c1_pins_a: i2c1 at 0 {
> -				allwinner,pins = "PH4", "PH5";
> -				allwinner,function = "i2c1";
> -				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> -				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +				pins = "PH4", "PH5";
> +				function = "i2c1";
>   			};
>   
>   			i2c2_pins_a: i2c2 at 0 {
> -				allwinner,pins = "PE12", "PE13";
> -				allwinner,function = "i2c2";
> -				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> -				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +				pins = "PE12", "PE13";
> +				function = "i2c2";
>   			};
> -		};
> -
> -		ahb1_rst: reset at 01c202c0 {
> -			#reset-cells = <1>;
> -			compatible = "allwinner,sun6i-a31-clock-reset";
> -			reg = <0x01c202c0 0xc>;
> -		};
>   
> -		apb1_rst: reset at 01c202d0 {
> -			#reset-cells = <1>;
> -			compatible = "allwinner,sun6i-a31-clock-reset";
> -			reg = <0x01c202d0 0x4>;
> -		};
> -
> -		apb2_rst: reset at 01c202d8 {
> -			#reset-cells = <1>;
> -			compatible = "allwinner,sun6i-a31-clock-reset";
> -			reg = <0x01c202d8 0x4>;
> +			lcd_rgb666_pins: lcd-rgb666 at 0 {
> +				pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
> +				       "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
> +				       "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
> +				       "PD24", "PD25", "PD26", "PD27";
> +				function = "lcd0";
> +			};
>   		};
>   
>   		timer at 01c20c00 {
> @@ -472,8 +379,8 @@
>   			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
>   			reg-shift = <2>;
>   			reg-io-width = <4>;
> -			clocks = <&apb2_gates 16>;
> -			resets = <&apb2_rst 16>;
> +			clocks = <&ccu CLK_BUS_UART0>;
> +			resets = <&ccu RST_BUS_UART0>;
>   			dmas = <&dma 6>, <&dma 6>;
>   			dma-names = "rx", "tx";
>   			status = "disabled";
> @@ -485,8 +392,8 @@
>   			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
>   			reg-shift = <2>;
>   			reg-io-width = <4>;
> -			clocks = <&apb2_gates 17>;
> -			resets = <&apb2_rst 17>;
> +			clocks = <&ccu CLK_BUS_UART1>;
> +			resets = <&ccu RST_BUS_UART1>;
>   			dmas = <&dma 7>, <&dma 7>;
>   			dma-names = "rx", "tx";
>   			status = "disabled";
> @@ -498,8 +405,8 @@
>   			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
>   			reg-shift = <2>;
>   			reg-io-width = <4>;
> -			clocks = <&apb2_gates 18>;
> -			resets = <&apb2_rst 18>;
> +			clocks = <&ccu CLK_BUS_UART2>;
> +			resets = <&ccu RST_BUS_UART2>;
>   			dmas = <&dma 8>, <&dma 8>;
>   			dma-names = "rx", "tx";
>   			status = "disabled";
> @@ -511,8 +418,8 @@
>   			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
>   			reg-shift = <2>;
>   			reg-io-width = <4>;
> -			clocks = <&apb2_gates 19>;
> -			resets = <&apb2_rst 19>;
> +			clocks = <&ccu CLK_BUS_UART3>;
> +			resets = <&ccu RST_BUS_UART3>;
>   			dmas = <&dma 9>, <&dma 9>;
>   			dma-names = "rx", "tx";
>   			status = "disabled";
> @@ -524,8 +431,8 @@
>   			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
>   			reg-shift = <2>;
>   			reg-io-width = <4>;
> -			clocks = <&apb2_gates 20>;
> -			resets = <&apb2_rst 20>;
> +			clocks = <&ccu CLK_BUS_UART4>;
> +			resets = <&ccu RST_BUS_UART4>;
>   			dmas = <&dma 10>, <&dma 10>;
>   			dma-names = "rx", "tx";
>   			status = "disabled";
> @@ -535,8 +442,8 @@
>   			compatible = "allwinner,sun6i-a31-i2c";
>   			reg = <0x01c2ac00 0x400>;
>   			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&apb2_gates 0>;
> -			resets = <&apb2_rst 0>;
> +			clocks = <&ccu CLK_BUS_I2C0>;
> +			resets = <&ccu RST_BUS_I2C0>;
>   			status = "disabled";
>   			#address-cells = <1>;
>   			#size-cells = <0>;
> @@ -546,8 +453,8 @@
>   			compatible = "allwinner,sun6i-a31-i2c";
>   			reg = <0x01c2b000 0x400>;
>   			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&apb2_gates 1>;
> -			resets = <&apb2_rst 1>;
> +			clocks = <&ccu CLK_BUS_I2C1>;
> +			resets = <&ccu RST_BUS_I2C1>;
>   			status = "disabled";
>   			#address-cells = <1>;
>   			#size-cells = <0>;
> @@ -557,17 +464,44 @@
>   			compatible = "allwinner,sun6i-a31-i2c";
>   			reg = <0x01c2b400 0x400>;
>   			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&apb2_gates 2>;
> -			resets = <&apb2_rst 2>;
> +			clocks = <&ccu CLK_BUS_I2C2>;
> +			resets = <&ccu RST_BUS_I2C2>;
>   			status = "disabled";
>   			#address-cells = <1>;
>   			#size-cells = <0>;
>   		};
>   
> +		mali: gpu at 1c40000 {
> +			compatible = "allwinner,sun8i-a23-mali",
> +				     "allwinner,sun7i-a20-mali", "arm,mali-400";
> +			reg = <0x01c40000 0x10000>;
> +			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "gp",
> +					  "gpmmu",
> +					  "pp0",
> +					  "ppmmu0",
> +					  "pp1",
> +					  "ppmmu1",
> +					  "pmu";
> +			clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
> +			clock-names = "bus", "core";
> +			resets = <&ccu RST_BUS_GPU>;
> +			#cooling-cells = <2>;
> +
> +			assigned-clocks = <&ccu CLK_GPU>;
> +			assigned-clock-rates = <384000000>;
> +		};
> +
>   		gic: interrupt-controller at 01c81000 {
>   			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
>   			reg = <0x01c81000 0x1000>,
> -			      <0x01c82000 0x1000>,
> +			      <0x01c82000 0x2000>,
>   			      <0x01c84000 0x2000>,
>   			      <0x01c86000 0x2000>;
>   			interrupt-controller;
> @@ -580,13 +514,16 @@
>   			reg = <0x01f00000 0x54>;
>   			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
>   				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-output-names = "osc32k";
> +			clocks = <&ext_osc32k>;
> +			#clock-cells = <1>;
>   		};
>   
> -		nmi_intc: interrupt-controller at 01f00c0c {
> -			compatible = "allwinner,sun6i-a31-sc-nmi";
> +		nmi_intc: interrupt-controller at 1f00c00 {
> +			compatible = "allwinner,sun6i-a31-r-intc";
>   			interrupt-controller;
>   			#interrupt-cells = <2>;
> -			reg = <0x01f00c0c 0x38>;
> +			reg = <0x01f00c00 0x400>;
>   			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
>   		};
>   
> @@ -632,6 +569,10 @@
>   				compatible = "allwinner,sun6i-a31-clock-reset";
>   				#reset-cells = <1>;
>   			};
> +
> +			codec_analog: codec-analog {
> +				compatible = "allwinner,sun8i-a23-codec-analog";
> +			};
>   		};
>   
>   		cpucfg at 01f01c00 {
> @@ -654,7 +595,8 @@
>   			compatible = "allwinner,sun8i-a23-r-pinctrl";
>   			reg = <0x01f02c00 0x400>;
>   			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&apb0_gates 0>;
> +			clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
> +			clock-names = "apb", "hosc", "losc";
>   			resets = <&apb0_rst 0>;
>   			gpio-controller;
>   			interrupt-controller;
> @@ -664,17 +606,15 @@
>   			#gpio-cells = <3>;
>   
>   			r_rsb_pins: r_rsb {
> -				allwinner,pins = "PL0", "PL1";
> -				allwinner,function = "s_rsb";
> -				allwinner,drive = <SUN4I_PINCTRL_20_MA>;
> -				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
> +				pins = "PL0", "PL1";
> +				function = "s_rsb";
> +				drive-strength = <20>;
> +				bias-pull-up;
>   			};
>   
>   			r_uart_pins_a: r_uart at 0 {
> -				allwinner,pins = "PL2", "PL3";
> -				allwinner,function = "s_uart";
> -				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> -				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +				pins = "PL2", "PL3";
> +				function = "s_uart";
>   			};
>   		};
>   
> diff --git a/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts
> index fef6abc0a703..b1bc88c46c67 100644
> --- a/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts
> +++ b/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts
> @@ -61,6 +61,31 @@
>   	chosen {
>   		stdout-path = "serial0:115200n8";
>   	};
> +
> +	panel {
> +		compatible = "netron-dy,e231732";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		port at 0 {
> +			reg = <0>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			panel_input: endpoint at 0 {
> +				reg = <0>;
> +				remote-endpoint = <&tcon0_out_panel>;
> +			};
> +		};
> +	};
> +};
> +
> +&de {
> +	status = "okay";
> +};
> +
> +&cpu0 {
> +	cpu-supply = <&reg_dcdc3>;
>   };
>   
>   &ehci0 {
> @@ -207,12 +232,30 @@
>   	regulator-name = "vcc-rtc";
>   };
>   
> +&tcon0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&lcd_rgb666_pins>;
> +	status = "okay";
> +};
> +
> +&tcon0_out {
> +	tcon0_out_panel: endpoint at 0 {
> +		reg = <0>;
> +		remote-endpoint = <&panel_input>;
> +	};
> +};
> +
>   &uart0 {
>   	pinctrl-names = "default";
>   	pinctrl-0 = <&uart0_pins_b>;
>   	status = "okay";
>   };
>   
> +&usb_otg {
> +	dr_mode = "peripheral";
> +	status = "okay";
> +};
> +
>   &usbphy {
>   	status = "okay";
>   	usb1_vbus-supply = <&reg_vcc5v0>; /* USB1 VBUS is always on */
> diff --git a/arch/arm/dts/sun8i-a33.dtsi b/arch/arm/dts/sun8i-a33.dtsi
> index 001d8402ca18..22660919bd08 100644
> --- a/arch/arm/dts/sun8i-a33.dtsi
> +++ b/arch/arm/dts/sun8i-a33.dtsi
> @@ -43,19 +43,137 @@
>    */
>   
>   #include "sun8i-a23-a33.dtsi"
> +#include <dt-bindings/thermal/thermal.h>
>   
>   / {
> +	cpu0_opp_table: opp_table0 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp-120000000 {
> +			opp-hz = /bits/ 64 <120000000>;
> +			opp-microvolt = <1040000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +
> +		opp-240000000 {
> +			opp-hz = /bits/ 64 <240000000>;
> +			opp-microvolt = <1040000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +
> +		opp-312000000 {
> +			opp-hz = /bits/ 64 <312000000>;
> +			opp-microvolt = <1040000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +
> +		opp-408000000 {
> +			opp-hz = /bits/ 64 <408000000>;
> +			opp-microvolt = <1040000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +
> +		opp-480000000 {
> +			opp-hz = /bits/ 64 <480000000>;
> +			opp-microvolt = <1040000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +
> +		opp-504000000 {
> +			opp-hz = /bits/ 64 <504000000>;
> +			opp-microvolt = <1040000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +
> +		opp-600000000 {
> +			opp-hz = /bits/ 64 <600000000>;
> +			opp-microvolt = <1040000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +
> +		opp-648000000 {
> +			opp-hz = /bits/ 64 <648000000>;
> +			opp-microvolt = <1040000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +
> +		opp-720000000 {
> +			opp-hz = /bits/ 64 <720000000>;
> +			opp-microvolt = <1100000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +
> +		opp-816000000 {
> +			opp-hz = /bits/ 64 <816000000>;
> +			opp-microvolt = <1100000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +
> +		opp-912000000 {
> +			opp-hz = /bits/ 64 <912000000>;
> +			opp-microvolt = <1200000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +
> +		opp-1008000000 {
> +			opp-hz = /bits/ 64 <1008000000>;
> +			opp-microvolt = <1200000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +	};
> +
>   	cpus {
> +		cpu at 0 {
> +			clocks = <&ccu CLK_CPUX>;
> +			clock-names = "cpu";
> +			operating-points-v2 = <&cpu0_opp_table>;
> +			#cooling-cells = <2>;
> +		};
> +
> +		cpu at 1 {
> +			operating-points-v2 = <&cpu0_opp_table>;
> +		};
> +
>   		cpu at 2 {
>   			compatible = "arm,cortex-a7";
>   			device_type = "cpu";
>   			reg = <2>;
> +			operating-points-v2 = <&cpu0_opp_table>;
>   		};
>   
>   		cpu at 3 {
>   			compatible = "arm,cortex-a7";
>   			device_type = "cpu";
>   			reg = <3>;
> +			operating-points-v2 = <&cpu0_opp_table>;
> +		};
> +	};
> +
> +	de: display-engine {
> +		compatible = "allwinner,sun8i-a33-display-engine";
> +		allwinner,pipelines = <&fe0>;
> +		status = "disabled";
> +	};
> +
> +	iio-hwmon {
> +		compatible = "iio-hwmon";
> +		io-channels = <&ths>;
> +	};
> +
> +	mali_opp_table: gpu-opp-table {
> +		compatible = "operating-points-v2";
> +
> +		opp-144000000 {
> +			opp-hz = /bits/ 64 <144000000>;
> +		};
> +
> +		opp-240000000 {
> +			opp-hz = /bits/ 64 <240000000>;
> +		};
> +
> +		opp-384000000 {
> +			opp-hz = /bits/ 64 <384000000>;
>   		};
>   	};
>   
> @@ -63,113 +181,310 @@
>   		reg = <0x40000000 0x80000000>;
>   	};
>   
> -	clocks {
> -		/* Dummy clock for pll11 (DDR1) until actually implemented */
> -		pll11: pll11_clk {
> -			#clock-cells = <0>;
> -			compatible = "fixed-clock";
> -			clock-frequency = <0>;
> -			clock-output-names = "pll11";
> -		};
> -
> -		ahb1_gates: clk at 01c20060 {
> -			#clock-cells = <1>;
> -			compatible = "allwinner,sun8i-a33-ahb1-gates-clk";
> -			reg = <0x01c20060 0x8>;
> -			clocks = <&ahb1>;
> -			clock-indices = <1>, <5>,
> -				        <6>, <8>, <9>,
> -				        <10>, <13>, <14>,
> -					<19>, <20>,
> -					<21>, <24>, <26>,
> -					<29>, <32>, <36>,
> -					<40>, <44>, <46>,
> -					<52>, <53>,
> -					<54>, <57>,
> -					<58>;
> -			clock-output-names = "ahb1_mipidsi", "ahb1_ss",
> -					"ahb1_dma","ahb1_mmc0", "ahb1_mmc1",
> -					"ahb1_mmc2", "ahb1_nand", "ahb1_sdram",
> -					"ahb1_hstimer", "ahb1_spi0",
> -					"ahb1_spi1", "ahb1_otg", "ahb1_ehci",
> -					"ahb1_ohci", "ahb1_ve", "ahb1_lcd",
> -					"ahb1_csi", "ahb1_be",	"ahb1_fe",
> -					"ahb1_gpu", "ahb1_msgbox",
> -					"ahb1_spinlock", "ahb1_drc",
> -					"ahb1_sat";
> -		};
> -
> -		ss_clk: clk at 01c2009c {
> -			#clock-cells = <0>;
> -			compatible = "allwinner,sun4i-a10-mod0-clk";
> -			reg = <0x01c2009c 0x4>;
> -			clocks = <&osc24M>, <&pll6 0>;
> -			clock-output-names = "ss";
> -		};
> -
> -		mbus_clk: clk at 01c2015c {
> -			#clock-cells = <0>;
> -			compatible = "allwinner,sun8i-a23-mbus-clk";
> -			reg = <0x01c2015c 0x4>;
> -			clocks = <&osc24M>, <&pll6 1>, <&pll5>, <&pll11>;
> -			clock-output-names = "mbus";
> +	sound: sound {
> +		compatible = "simple-audio-card";
> +		simple-audio-card,name = "sun8i-a33-audio";
> +		simple-audio-card,format = "i2s";
> +		simple-audio-card,frame-master = <&link_codec>;
> +		simple-audio-card,bitclock-master = <&link_codec>;
> +		simple-audio-card,mclk-fs = <512>;
> +		simple-audio-card,aux-devs = <&codec_analog>;
> +		simple-audio-card,routing =
> +			"Left DAC", "AIF1 Slot 0 Left",
> +			"Right DAC", "AIF1 Slot 0 Right";
> +		status = "disabled";
> +
> +		simple-audio-card,cpu {
> +			sound-dai = <&dai>;
> +		};
> +
> +		link_codec: simple-audio-card,codec {
> +			sound-dai = <&codec>;
>   		};
>   	};
>   
>   	soc at 01c00000 {
> +		tcon0: lcd-controller at 01c0c000 {
> +			compatible = "allwinner,sun8i-a33-tcon";
> +			reg = <0x01c0c000 0x1000>;
> +			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_LCD>,
> +				 <&ccu CLK_LCD_CH0>;
> +			clock-names = "ahb",
> +				      "tcon-ch0";
> +			clock-output-names = "tcon-pixel-clock";
> +			resets = <&ccu RST_BUS_LCD>;
> +			reset-names = "lcd";
> +			status = "disabled";
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				tcon0_in: port at 0 {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					reg = <0>;
> +
> +					tcon0_in_drc0: endpoint at 0 {
> +						reg = <0>;
> +						remote-endpoint = <&drc0_out_tcon0>;
> +					};
> +				};
> +
> +				tcon0_out: port at 1 {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					reg = <1>;
> +				};
> +			};
> +		};
> +
>   		crypto: crypto-engine at 01c15000 {
>   			compatible = "allwinner,sun4i-a10-crypto";
>   			reg = <0x01c15000 0x1000>;
>   			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&ahb1_gates 5>, <&ss_clk>;
> +			clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
>   			clock-names = "ahb", "mod";
> -			resets = <&ahb1_rst 5>;
> +			resets = <&ccu RST_BUS_SS>;
>   			reset-names = "ahb";
>   		};
>   
> -		usb_otg: usb at 01c19000 {
> -			compatible = "allwinner,sun8i-a33-musb";
> -			reg = <0x01c19000 0x0400>;
> -			clocks = <&ahb1_gates 24>;
> -			resets = <&ahb1_rst 24>;
> -			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> -			interrupt-names = "mc";
> -			phys = <&usbphy 0>;
> -			phy-names = "usb";
> -			extcon = <&usbphy 0>;
> +		dai: dai at 01c22c00 {
> +			#sound-dai-cells = <0>;
> +			compatible = "allwinner,sun6i-a31-i2s";
> +			reg = <0x01c22c00 0x200>;
> +			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
> +			clock-names = "apb", "mod";
> +			resets = <&ccu RST_BUS_CODEC>;
> +			dmas = <&dma 15>, <&dma 15>;
> +			dma-names = "rx", "tx";
> +			status = "disabled";
> +		};
> +
> +		codec: codec at 01c22e00 {
> +			#sound-dai-cells = <0>;
> +			compatible = "allwinner,sun8i-a33-codec";
> +			reg = <0x01c22e00 0x400>;
> +			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
> +			clock-names = "bus", "mod";
>   			status = "disabled";
>   		};
>   
> -		usbphy: phy at 01c19400 {
> -			compatible = "allwinner,sun8i-a33-usb-phy";
> -			reg = <0x01c19400 0x14>,
> -			      <0x01c1a800 0x4>;
> -			reg-names = "phy_ctrl",
> -				    "pmu1";
> -			clocks = <&usb_clk 8>,
> -				 <&usb_clk 9>;
> -			clock-names = "usb0_phy",
> -				      "usb1_phy";
> -			resets = <&usb_clk 0>,
> -				 <&usb_clk 1>;
> -			reset-names = "usb0_reset",
> -				      "usb1_reset";
> +		ths: ths at 01c25000 {
> +			compatible = "allwinner,sun8i-a33-ths";
> +			reg = <0x01c25000 0x100>;
> +			#thermal-sensor-cells = <0>;
> +			#io-channel-cells = <0>;
> +		};
> +
> +		fe0: display-frontend at 01e00000 {
> +			compatible = "allwinner,sun8i-a33-display-frontend";
> +			reg = <0x01e00000 0x20000>;
> +			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
> +				 <&ccu CLK_DRAM_DE_FE>;
> +			clock-names = "ahb", "mod",
> +				      "ram";
> +			resets = <&ccu RST_BUS_DE_FE>;
>   			status = "disabled";
> -			#phy-cells = <1>;
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				fe0_out: port at 1 {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					reg = <1>;
> +
> +					fe0_out_be0: endpoint at 0 {
> +						reg = <0>;
> +						remote-endpoint = <&be0_in_fe0>;
> +					};
> +				};
> +			};
> +		};
> +
> +		be0: display-backend at 01e60000 {
> +			compatible = "allwinner,sun8i-a33-display-backend";
> +			reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
> +			reg-names = "be", "sat";
> +			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
> +				 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
> +			clock-names = "ahb", "mod",
> +				      "ram", "sat";
> +			resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
> +			reset-names = "be", "sat";
> +			assigned-clocks = <&ccu CLK_DE_BE>;
> +			assigned-clock-rates = <300000000>;
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				be0_in: port at 0 {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					reg = <0>;
> +
> +					be0_in_fe0: endpoint at 0 {
> +						reg = <0>;
> +						remote-endpoint = <&fe0_out_be0>;
> +					};
> +				};
> +
> +				be0_out: port at 1 {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					reg = <1>;
> +
> +					be0_out_drc0: endpoint at 0 {
> +						reg = <0>;
> +						remote-endpoint = <&drc0_in_be0>;
> +					};
> +				};
> +			};
> +		};
> +
> +		drc0: drc at 01e70000 {
> +			compatible = "allwinner,sun8i-a33-drc";
> +			reg = <0x01e70000 0x10000>;
> +			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
> +				 <&ccu CLK_DRAM_DRC>;
> +			clock-names = "ahb", "mod", "ram";
> +			resets = <&ccu RST_BUS_DRC>;
> +
> +			assigned-clocks = <&ccu CLK_DRC>;
> +			assigned-clock-rates = <300000000>;
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				drc0_in: port at 0 {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					reg = <0>;
> +
> +					drc0_in_be0: endpoint at 0 {
> +						reg = <0>;
> +						remote-endpoint = <&be0_out_drc0>;
> +					};
> +				};
> +
> +				drc0_out: port at 1 {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					reg = <1>;
> +
> +					drc0_out_tcon0: endpoint at 0 {
> +						reg = <0>;
> +						remote-endpoint = <&tcon0_in_drc0>;
> +					};
> +				};
> +			};
> +		};
> +	};
> +
> +	thermal-zones {
> +		cpu_thermal {
> +			/* milliseconds */
> +			polling-delay-passive = <250>;
> +			polling-delay = <1000>;
> +			thermal-sensors = <&ths>;
> +
> +			cooling-maps {
> +				map0 {
> +					trip = <&cpu_alert0>;
> +					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +				map1 {
> +					trip = <&cpu_alert1>;
> +					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +
> +				map2 {
> +					trip = <&gpu_alert0>;
> +					cooling-device = <&mali 1 THERMAL_NO_LIMIT>;
> +				};
> +
> +				map3 {
> +					trip = <&gpu_alert1>;
> +					cooling-device = <&mali 2 THERMAL_NO_LIMIT>;
> +				};
> +			};
> +
> +			trips {
> +				cpu_alert0: cpu_alert0 {
> +					/* milliCelsius */
> +					temperature = <75000>;
> +					hysteresis = <2000>;
> +					type = "passive";
> +				};
> +
> +				gpu_alert0: gpu_alert0 {
> +					/* milliCelsius */
> +					temperature = <85000>;
> +					hysteresis = <2000>;
> +					type = "passive";
> +				};
> +
> +				cpu_alert1: cpu_alert1 {
> +					/* milliCelsius */
> +					temperature = <90000>;
> +					hysteresis = <2000>;
> +					type = "hot";
> +				};
> +
> +				gpu_alert1: gpu_alert1 {
> +					/* milliCelsius */
> +					temperature = <95000>;
> +					hysteresis = <2000>;
> +					type = "hot";
> +				};
> +
> +				cpu_crit: cpu_crit {
> +					/* milliCelsius */
> +					temperature = <110000>;
> +					hysteresis = <2000>;
> +					type = "critical";
> +				};
> +			};
>   		};
>   	};
>   };
>   
> +&ccu {
> +	compatible = "allwinner,sun8i-a33-ccu";
> +};
> +
> +&mali {
> +	operating-points-v2 = <&mali_opp_table>;
> +};
> +
>   &pio {
>   	compatible = "allwinner,sun8i-a33-pinctrl";
>   	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
>   		     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
>   
>   	uart0_pins_b: uart0 at 1 {
> -		allwinner,pins = "PB0", "PB1";
> -		allwinner,function = "uart0";
> -		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> -		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +		pins = "PB0", "PB1";
> +		function = "uart0";
>   	};
>   
>   };
> +
> +&usb_otg {
> +	compatible = "allwinner,sun8i-a33-musb";
> +};
> +
> +&usbphy {
> +	compatible = "allwinner,sun8i-a33-usb-phy";
> +	reg = <0x01c19400 0x14>, <0x01c1a800 0x4>;
> +	reg-names = "phy_ctrl", "pmu1";
> +};
> diff --git a/include/dt-bindings/clock/sun8i-a23-a33-ccu.h b/include/dt-bindings/clock/sun8i-a23-a33-ccu.h
> new file mode 100644
> index 000000000000..f8222b6b2cc3
> --- /dev/null
> +++ b/include/dt-bindings/clock/sun8i-a23-a33-ccu.h
> @@ -0,0 +1,127 @@
> +/*
> + * Copyright (C) 2016 Maxime Ripard <maxime.ripard at free-electrons.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This file is distributed in the hope that it will be useful,
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use,
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_SUN8I_A23_A33_H_
> +#define _DT_BINDINGS_CLK_SUN8I_A23_A33_H_
> +
> +#define CLK_CPUX		18
> +
> +#define CLK_BUS_MIPI_DSI	23
> +#define CLK_BUS_SS		24
> +#define CLK_BUS_DMA		25
> +#define CLK_BUS_MMC0		26
> +#define CLK_BUS_MMC1		27
> +#define CLK_BUS_MMC2		28
> +#define CLK_BUS_NAND		29
> +#define CLK_BUS_DRAM		30
> +#define CLK_BUS_HSTIMER		31
> +#define CLK_BUS_SPI0		32
> +#define CLK_BUS_SPI1		33
> +#define CLK_BUS_OTG		34
> +#define CLK_BUS_EHCI		35
> +#define CLK_BUS_OHCI		36
> +#define CLK_BUS_VE		37
> +#define CLK_BUS_LCD		38
> +#define CLK_BUS_CSI		39
> +#define CLK_BUS_DE_BE		40
> +#define CLK_BUS_DE_FE		41
> +#define CLK_BUS_GPU		42
> +#define CLK_BUS_MSGBOX		43
> +#define CLK_BUS_SPINLOCK	44
> +#define CLK_BUS_DRC		45
> +#define CLK_BUS_SAT		46
> +#define CLK_BUS_CODEC		47
> +#define CLK_BUS_PIO		48
> +#define CLK_BUS_I2S0		49
> +#define CLK_BUS_I2S1		50
> +#define CLK_BUS_I2C0		51
> +#define CLK_BUS_I2C1		52
> +#define CLK_BUS_I2C2		53
> +#define CLK_BUS_UART0		54
> +#define CLK_BUS_UART1		55
> +#define CLK_BUS_UART2		56
> +#define CLK_BUS_UART3		57
> +#define CLK_BUS_UART4		58
> +#define CLK_NAND		59
> +#define CLK_MMC0		60
> +#define CLK_MMC0_SAMPLE		61
> +#define CLK_MMC0_OUTPUT		62
> +#define CLK_MMC1		63
> +#define CLK_MMC1_SAMPLE		64
> +#define CLK_MMC1_OUTPUT		65
> +#define CLK_MMC2		66
> +#define CLK_MMC2_SAMPLE		67
> +#define CLK_MMC2_OUTPUT		68
> +#define CLK_SS			69
> +#define CLK_SPI0		70
> +#define CLK_SPI1		71
> +#define CLK_I2S0		72
> +#define CLK_I2S1		73
> +#define CLK_USB_PHY0		74
> +#define CLK_USB_PHY1		75
> +#define CLK_USB_HSIC		76
> +#define CLK_USB_HSIC_12M	77
> +#define CLK_USB_OHCI		78
> +
> +#define CLK_DRAM_VE		80
> +#define CLK_DRAM_CSI		81
> +#define CLK_DRAM_DRC		82
> +#define CLK_DRAM_DE_FE		83
> +#define CLK_DRAM_DE_BE		84
> +#define CLK_DE_BE		85
> +#define CLK_DE_FE		86
> +#define CLK_LCD_CH0		87
> +#define CLK_LCD_CH1		88
> +#define CLK_CSI_SCLK		89
> +#define CLK_CSI_MCLK		90
> +#define CLK_VE			91
> +#define CLK_AC_DIG		92
> +#define CLK_AC_DIG_4X		93
> +#define CLK_AVS			94
> +
> +#define CLK_DSI_SCLK		96
> +#define CLK_DSI_DPHY		97
> +#define CLK_DRC			98
> +#define CLK_GPU			99
> +#define CLK_ATS			100
> +
> +#endif /* _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ */
> diff --git a/include/dt-bindings/reset/sun8i-a23-a33-ccu.h b/include/dt-bindings/reset/sun8i-a23-a33-ccu.h
> new file mode 100644
> index 000000000000..6121f2b0cd0a
> --- /dev/null
> +++ b/include/dt-bindings/reset/sun8i-a23-a33-ccu.h
> @@ -0,0 +1,87 @@
> +/*
> + * Copyright (C) 2016 Maxime Ripard <maxime.ripard at free-electrons.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This file is distributed in the hope that it will be useful,
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use,
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
Shouldn't we use the SPDX license header?

Tom what is the policy for importing dts[i] files from Linux kernel?

> +
> +#ifndef _DT_BINDINGS_RST_SUN8I_A23_A33_H_
> +#define _DT_BINDINGS_RST_SUN8I_A23_A33_H_
> +
> +#define RST_USB_PHY0		0
> +#define RST_USB_PHY1		1
> +#define RST_USB_HSIC		2
> +#define RST_MBUS		3
> +#define RST_BUS_MIPI_DSI	4
> +#define RST_BUS_SS		5
> +#define RST_BUS_DMA		6
> +#define RST_BUS_MMC0		7
> +#define RST_BUS_MMC1		8
> +#define RST_BUS_MMC2		9
> +#define RST_BUS_NAND		10
> +#define RST_BUS_DRAM		11
> +#define RST_BUS_HSTIMER		12
> +#define RST_BUS_SPI0		13
> +#define RST_BUS_SPI1		14
> +#define RST_BUS_OTG		15
> +#define RST_BUS_EHCI		16
> +#define RST_BUS_OHCI		17
> +#define RST_BUS_VE		18
> +#define RST_BUS_LCD		19
> +#define RST_BUS_CSI		20
> +#define RST_BUS_DE_BE		21
> +#define RST_BUS_DE_FE		22
> +#define RST_BUS_GPU		23
> +#define RST_BUS_MSGBOX		24
> +#define RST_BUS_SPINLOCK	25
> +#define RST_BUS_DRC		26
> +#define RST_BUS_SAT		27
> +#define RST_BUS_LVDS		28
> +#define RST_BUS_CODEC		29
> +#define RST_BUS_I2S0		30
> +#define RST_BUS_I2S1		31
> +#define RST_BUS_I2C0		32
> +#define RST_BUS_I2C1		33
> +#define RST_BUS_I2C2		34
> +#define RST_BUS_UART0		35
> +#define RST_BUS_UART1		36
> +#define RST_BUS_UART2		37
> +#define RST_BUS_UART3		38
> +#define RST_BUS_UART4		39
> +
> +#endif /* _DT_BINDINGS_RST_SUN8I_A23_A33_H_ */
> 

Reviewed-by: Łukasz Majewski <lukma at denx.de>

-- 
Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de



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