[U-Boot] [PATCH v2 8/9] ARM: DTS: stm32: adapt stm32h7 dts files for U-boot
patrice.chotard at st.com
patrice.chotard at st.com
Wed Sep 13 16:00:11 UTC 2017
From: Patrice Chotard <patrice.chotard at st.com>
This patch adapts stm32h743 disco and eval dts files to match
with U-boot requirements or add features wich are not yet
upstreamed on kernel side :
_ Add RCC clock driver node and update all clocks phandle
accordingly.
By default, on kernel side, all clocks was temporarly
configured as a phandle to timer_clk waiting for a RCC
clock driver to be available.
On U-boot side, we now have a dedicated RCC clock driver, we
can configured all clocks as phandle to this driver.
All this binding update will be available soon in a kernel tag,
as all the bindings have been acked by Rob Herring [1].
[1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html
_ Align STM32H7 serial compatible string with the one which will be
available in next kernel tag. The bindings has been acked by
Rob Herring [2].
This compatible string will be usefull to add stm32h7 specific
feature for this serial driver.
[2] https://lkml.org/lkml/2017/7/17/739
_ Add gpio compatible and aliases for stm32h743
_ Add FMC sdram node with associated new bindings value to
manage second bank (ie bank 1).
_ Add missing HSI and CSI oscillators nodes needed
by STM32H7 RCC clock driver.
Clock sources could be:
_ HSE (High Speed External)
_ HSI (High Speed Internal)
_ CSI (Low Power Internal)
These clocks can be used as clocksource in some configuration.
By default, HSE is selected as clock source.
_ Set HSE to 25Mhz for stm32h743i-disco and eval board
By default, the external oscillator frequency is defined at
25 Mhz in SoC stm32h743.dtsi file.
It has been set at 125 Mhz in kernel DT temporarly waiting for
RCC clock driver becomes available.
As in U-boot we got a RCC clock driver, the real value of HSE
clock can be used.
_ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl,
pwrcfg and gpio nodes.
Signed-off-by: Patrice Chotard <patrice.chotard at st.com>
---
arch/arm/dts/stm32h7-u-boot.dtsi | 88 ++++++++++++++++++++++++++
arch/arm/dts/stm32h743-pinctrl.dtsi | 102 +++++++++++++++++++++++++++----
arch/arm/dts/stm32h743.dtsi | 56 ++++++++++++++---
arch/arm/dts/stm32h743i-disco.dts | 35 +++++++++--
arch/arm/dts/stm32h743i-eval.dts | 34 +++++++++--
include/dt-bindings/memory/stm32-sdram.h | 7 +++
6 files changed, 294 insertions(+), 28 deletions(-)
create mode 100644 arch/arm/dts/stm32h7-u-boot.dtsi
diff --git a/arch/arm/dts/stm32h7-u-boot.dtsi b/arch/arm/dts/stm32h7-u-boot.dtsi
new file mode 100644
index 0000000..2525035
--- /dev/null
+++ b/arch/arm/dts/stm32h7-u-boot.dtsi
@@ -0,0 +1,88 @@
+/{
+ clocks {
+ u-boot,dm-pre-reloc;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ pin-controller {
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
+
+&clk_hse {
+ u-boot,dm-pre-reloc;
+};
+
+&clk_lse {
+ u-boot,dm-pre-reloc;
+};
+
+&clk_i2s {
+ u-boot,dm-pre-reloc;
+};
+
+&pwrcfg {
+ u-boot,dm-pre-reloc;
+};
+
+&rcc {
+ u-boot,dm-pre-reloc;
+};
+
+&fmc {
+ u-boot,dm-pre-reloc;
+};
+
+&clk_hsi {
+ u-boot,dm-pre-reloc;
+};
+
+&clk_csi {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioa {
+ u-boot,dm-pre-reloc;
+};
+
+&gpiob {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioc {
+ u-boot,dm-pre-reloc;
+};
+
+&gpiod {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioe {
+ u-boot,dm-pre-reloc;
+};
+
+&gpiof {
+ u-boot,dm-pre-reloc;
+};
+
+&gpiog {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioh {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioi {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioj {
+ u-boot,dm-pre-reloc;
+};
+
+&gpiok {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/stm32h743-pinctrl.dtsi b/arch/arm/dts/stm32h743-pinctrl.dtsi
index 76bbd65..d3e11d5 100644
--- a/arch/arm/dts/stm32h743-pinctrl.dtsi
+++ b/arch/arm/dts/stm32h743-pinctrl.dtsi
@@ -54,88 +54,99 @@
gpioa: gpio at 58020000 {
gpio-controller;
#gpio-cells = <2>;
+ compatible = "st,stm32-gpio";
reg = <0x0 0x400>;
- clocks = <&timer_clk>;
+ clocks = <&rcc GPIOA_CK>;
st,bank-name = "GPIOA";
};
gpiob: gpio at 58020400 {
gpio-controller;
#gpio-cells = <2>;
+ compatible = "st,stm32-gpio";
reg = <0x400 0x400>;
- clocks = <&timer_clk>;
+ clocks = <&rcc GPIOB_CK>;
st,bank-name = "GPIOB";
};
gpioc: gpio at 58020800 {
gpio-controller;
#gpio-cells = <2>;
+ compatible = "st,stm32-gpio";
reg = <0x800 0x400>;
- clocks = <&timer_clk>;
+ clocks = <&rcc GPIOC_CK>;
st,bank-name = "GPIOC";
};
gpiod: gpio at 58020c00 {
gpio-controller;
#gpio-cells = <2>;
+ compatible = "st,stm32-gpio";
reg = <0xc00 0x400>;
- clocks = <&timer_clk>;
+ clocks = <&rcc GPIOD_CK>;
st,bank-name = "GPIOD";
};
gpioe: gpio at 58021000 {
gpio-controller;
#gpio-cells = <2>;
+ compatible = "st,stm32-gpio";
reg = <0x1000 0x400>;
- clocks = <&timer_clk>;
+ clocks = <&rcc GPIOE_CK>;
st,bank-name = "GPIOE";
};
gpiof: gpio at 58021400 {
gpio-controller;
#gpio-cells = <2>;
+ compatible = "st,stm32-gpio";
reg = <0x1400 0x400>;
- clocks = <&timer_clk>;
+ clocks = <&rcc GPIOF_CK>;
st,bank-name = "GPIOF";
};
gpiog: gpio at 58021800 {
gpio-controller;
#gpio-cells = <2>;
+ compatible = "st,stm32-gpio";
reg = <0x1800 0x400>;
- clocks = <&timer_clk>;
+ clocks = <&rcc GPIOG_CK>;
st,bank-name = "GPIOG";
};
gpioh: gpio at 58021c00 {
gpio-controller;
#gpio-cells = <2>;
+ compatible = "st,stm32-gpio";
reg = <0x1c00 0x400>;
- clocks = <&timer_clk>;
+ clocks = <&rcc GPIOH_CK>;
st,bank-name = "GPIOH";
};
gpioi: gpio at 58022000 {
gpio-controller;
#gpio-cells = <2>;
+ compatible = "st,stm32-gpio";
reg = <0x2000 0x400>;
- clocks = <&timer_clk>;
+ clocks = <&rcc GPIOI_CK>;
st,bank-name = "GPIOI";
};
gpioj: gpio at 58022400 {
gpio-controller;
#gpio-cells = <2>;
+ compatible = "st,stm32-gpio";
reg = <0x2400 0x400>;
- clocks = <&timer_clk>;
+ clocks = <&rcc GPIOJ_CK>;
st,bank-name = "GPIOJ";
};
gpiok: gpio at 58022800 {
gpio-controller;
#gpio-cells = <2>;
+ compatible = "st,stm32-gpio";
reg = <0x2800 0x400>;
- clocks = <&timer_clk>;
+ clocks = <&rcc GPIOK_CK>;
st,bank-name = "GPIOK";
};
@@ -164,6 +175,75 @@
bias-disable;
};
};
+
+ fmc_pins: fmc at 0 {
+ pins {
+ pinmux = <STM32H7_PD0_FUNC_FMC_D2_FMC_DA2>,
+ <STM32H7_PD1_FUNC_FMC_D3_FMC_DA3>,
+ <STM32H7_PD8_FUNC_FMC_D13_FMC_DA13>,
+ <STM32H7_PD9_FUNC_FMC_D14_FMC_DA14>,
+ <STM32H7_PD10_FUNC_FMC_D15_FMC_DA15>,
+ <STM32H7_PD14_FUNC_FMC_D0_FMC_DA0>,
+ <STM32H7_PD15_FUNC_FMC_D1_FMC_DA1>,
+
+ <STM32H7_PE0_FUNC_FMC_NBL0>,
+ <STM32H7_PE1_FUNC_FMC_NBL1>,
+ <STM32H7_PE7_FUNC_FMC_D4_FMC_DA4>,
+ <STM32H7_PE8_FUNC_FMC_D5_FMC_DA5>,
+ <STM32H7_PE9_FUNC_FMC_D6_FMC_DA6>,
+ <STM32H7_PE10_FUNC_FMC_D7_FMC_DA7>,
+ <STM32H7_PE11_FUNC_FMC_D8_FMC_DA8>,
+ <STM32H7_PE12_FUNC_FMC_D9_FMC_DA9>,
+ <STM32H7_PE13_FUNC_FMC_D10_FMC_DA10>,
+ <STM32H7_PE14_FUNC_FMC_D11_FMC_DA11>,
+ <STM32H7_PE15_FUNC_FMC_D12_FMC_DA12>,
+
+ <STM32H7_PF0_FUNC_FMC_A0>,
+ <STM32H7_PF1_FUNC_FMC_A1>,
+ <STM32H7_PF2_FUNC_FMC_A2>,
+ <STM32H7_PF3_FUNC_FMC_A3>,
+ <STM32H7_PF4_FUNC_FMC_A4>,
+ <STM32H7_PF5_FUNC_FMC_A5>,
+ <STM32H7_PF11_FUNC_FMC_SDNRAS>,
+ <STM32H7_PF12_FUNC_FMC_A6>,
+ <STM32H7_PF13_FUNC_FMC_A7>,
+ <STM32H7_PF14_FUNC_FMC_A8>,
+ <STM32H7_PF15_FUNC_FMC_A9>,
+
+ <STM32H7_PG0_FUNC_FMC_A10>,
+ <STM32H7_PG1_FUNC_FMC_A11>,
+ <STM32H7_PG2_FUNC_FMC_A12>,
+ <STM32H7_PG4_FUNC_FMC_A14_FMC_BA0>,
+ <STM32H7_PG5_FUNC_FMC_A15_FMC_BA1>,
+ <STM32H7_PG8_FUNC_FMC_SDCLK>,
+ <STM32H7_PG15_FUNC_FMC_SDNCAS>,
+
+ <STM32H7_PH5_FUNC_FMC_SDNWE>,
+ <STM32H7_PH6_FUNC_FMC_SDNE1>,
+ <STM32H7_PH7_FUNC_FMC_SDCKE1>,
+ <STM32H7_PH8_FUNC_FMC_D16>,
+ <STM32H7_PH9_FUNC_FMC_D17>,
+ <STM32H7_PH10_FUNC_FMC_D18>,
+ <STM32H7_PH11_FUNC_FMC_D19>,
+ <STM32H7_PH12_FUNC_FMC_D20>,
+ <STM32H7_PH13_FUNC_FMC_D21>,
+ <STM32H7_PH14_FUNC_FMC_D22>,
+ <STM32H7_PH15_FUNC_FMC_D23>,
+
+ <STM32H7_PI0_FUNC_FMC_D24>,
+ <STM32H7_PI1_FUNC_FMC_D25>,
+ <STM32H7_PI2_FUNC_FMC_D26>,
+ <STM32H7_PI3_FUNC_FMC_D27>,
+ <STM32H7_PI4_FUNC_FMC_NBL2>,
+ <STM32H7_PI5_FUNC_FMC_NBL3>,
+ <STM32H7_PI6_FUNC_FMC_D28>,
+ <STM32H7_PI7_FUNC_FMC_D29>,
+ <STM32H7_PI9_FUNC_FMC_D30>,
+ <STM32H7_PI10_FUNC_FMC_D31>;
+
+ slew-rate = <3>;
+ };
+ };
};
};
};
diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi
index 36a99db..16e9308 100644
--- a/arch/arm/dts/stm32h743.dtsi
+++ b/arch/arm/dts/stm32h743.dtsi
@@ -42,45 +42,83 @@
#include "skeleton.dtsi"
#include "armv7-m.dtsi"
+#include <dt-bindings/clock/stm32h7-clks.h>
/ {
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "fixed-clock";
- clock-frequency = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ clk_lse: clk-lse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
};
- timer_clk: timer-clk {
+ clk_i2s: i2s_ckin {
#clock-cells = <0>;
compatible = "fixed-clock";
- clock-frequency = <125000000>;
+ clock-frequency = <0>;
};
};
soc {
+ rcc: rcc at 58024400 {
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ compatible = "st,stm32h743-rcc", "st,stm32-rcc";
+ reg = <0x58024400 0x400>;
+ clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>, <&clk_hsi>, <&clk_csi>;
+ st,syscfg = <&pwrcfg>;
+ };
+
usart1: serial at 40011000 {
- compatible = "st,stm32f7-usart", "st,stm32f7-uart";
+ compatible = "st,stm32h7-usart", "st,stm32h7-uart";
reg = <0x40011000 0x400>;
interrupts = <37>;
status = "disabled";
- clocks = <&timer_clk>;
-
+ clocks = <&rcc USART1_CK>;
};
usart2: serial at 40004400 {
- compatible = "st,stm32f7-usart", "st,stm32f7-uart";
+ compatible = "st,stm32h7-usart", "st,stm32h7-uart";
reg = <0x40004400 0x400>;
interrupts = <38>;
status = "disabled";
- clocks = <&timer_clk>;
+ clocks = <&rcc USART2_CK>;
};
timer5: timer at 40000c00 {
compatible = "st,stm32-timer";
reg = <0x40000c00 0x400>;
interrupts = <50>;
- clocks = <&timer_clk>;
+ clocks = <&rcc TIM5_CK>;
+ };
+
+ pwrcfg: power-config at 58024800 {
+ compatible = "syscon";
+ reg = <0x58024800 0x400>;
+ };
+
+ fmc: fmc at 52004000 {
+ compatible = "st,stm32h7-fmc";
+ reg = <0x52004000 0x1000>;
+ clocks = <&rcc FMC_CK>;
+ };
+
+ clk_hsi: clk-hsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <64000000>;
+ };
+
+ clk_csi: clk-csi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <4000000>;
};
};
};
diff --git a/arch/arm/dts/stm32h743i-disco.dts b/arch/arm/dts/stm32h743i-disco.dts
index 79e841d..bef7e90 100644
--- a/arch/arm/dts/stm32h743i-disco.dts
+++ b/arch/arm/dts/stm32h743i-disco.dts
@@ -43,6 +43,7 @@
/dts-v1/;
#include "stm32h743.dtsi"
#include "stm32h743-pinctrl.dtsi"
+#include <dt-bindings/memory/stm32-sdram.h>
/ {
model = "STMicroelectronics STM32H743i-Discovery board";
@@ -59,15 +60,41 @@
aliases {
serial0 = &usart2;
+ gpio0 = &gpioa;
+ gpio1 = &gpiob;
+ gpio2 = &gpioc;
+ gpio3 = &gpiod;
+ gpio4 = &gpioe;
+ gpio5 = &gpiof;
+ gpio6 = &gpiog;
+ gpio7 = &gpioh;
+ gpio8 = &gpioi;
+ gpio9 = &gpioj;
+ gpio10 = &gpiok;
};
};
-&clk_hse {
- clock-frequency = <125000000>;
-};
-
&usart2 {
pinctrl-0 = <&usart2_pins>;
pinctrl-names = "default";
status = "okay";
};
+
+&fmc {
+ pinctrl-0 = <&fmc_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /*
+ * Memory configuration from sdram datasheet IS42S32800G-6BLI
+ * firsct bank is bank at 0
+ * second bank is bank at 1
+ */
+ bank1: bank at 1 {
+ st,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32 BANKS_4
+ CAS_2 SDCLK_3 RD_BURST_EN RD_PIPE_DL_0>;
+ st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2
+ TWR_1 TRCD_1>;
+ st,sdram-refcount = <1539>;
+ };
+};
diff --git a/arch/arm/dts/stm32h743i-eval.dts b/arch/arm/dts/stm32h743i-eval.dts
index c6effbb..0e01ce5 100644
--- a/arch/arm/dts/stm32h743i-eval.dts
+++ b/arch/arm/dts/stm32h743i-eval.dts
@@ -43,6 +43,7 @@
/dts-v1/;
#include "stm32h743.dtsi"
#include "stm32h743-pinctrl.dtsi"
+#include <dt-bindings/memory/stm32-sdram.h>
/ {
model = "STMicroelectronics STM32H743i-EVAL board";
@@ -59,16 +60,41 @@
aliases {
serial0 = &usart1;
+ gpio0 = &gpioa;
+ gpio1 = &gpiob;
+ gpio2 = &gpioc;
+ gpio3 = &gpiod;
+ gpio4 = &gpioe;
+ gpio5 = &gpiof;
+ gpio6 = &gpiog;
+ gpio7 = &gpioh;
+ gpio8 = &gpioi;
+ gpio9 = &gpioj;
+ gpio10 = &gpiok;
};
};
-&clk_hse {
- clock-frequency = <125000000>;
-};
-
&usart1 {
pinctrl-0 = <&usart1_pins>;
pinctrl-names = "default";
status = "okay";
};
+&fmc {
+ pinctrl-0 = <&fmc_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /*
+ * Memory configuration from sdram datasheet IS42S32800G-6BLI
+ * firsct bank is bank at 0
+ * second bank is bank at 1
+ */
+ bank2: bank at 1 {
+ st,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32 BANKS_4
+ CAS_2 SDCLK_3 RD_BURST_EN RD_PIPE_DL_0>;
+ st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2
+ TWR_1 TRCD_1>;
+ st,sdram-refcount = <1539>;
+ };
+};
diff --git a/include/dt-bindings/memory/stm32-sdram.h b/include/dt-bindings/memory/stm32-sdram.h
index 89b719a..c2b911f 100644
--- a/include/dt-bindings/memory/stm32-sdram.h
+++ b/include/dt-bindings/memory/stm32-sdram.h
@@ -18,7 +18,9 @@
#define CAS_1 0x1
#define CAS_2 0x2
#define CAS_3 0x3
+#define SDCLK_DIS 0x0
#define SDCLK_2 0x2
+#define SDCLK_3 0x3
#define RD_BURST_EN 0x1
#define RD_BURST_DIS 0x0
#define RD_PIPE_DL_0 0x0
@@ -26,12 +28,17 @@
#define RD_PIPE_DL_2 0x2
/* Timing = value +1 cycles */
+#define TMRD_1 (1 - 1)
#define TMRD_2 (2 - 1)
+#define TXSR_1 (1 - 1)
#define TXSR_6 (6 - 1)
+#define TRAS_1 (1 - 1)
#define TRAS_4 (4 - 1)
#define TRC_6 (6 - 1)
+#define TWR_1 (1 - 1)
#define TWR_2 (2 - 1)
#define TRP_2 (2 - 1)
+#define TRCD_1 (1 - 1)
#define TRCD_2 (2 - 1)
#endif
--
1.9.1
More information about the U-Boot
mailing list