[U-Boot] [U-Boot, 6/8] clk: rockchip: Add rk3368 Saradc clock support

[Philipp Tomsich]

> The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
> Saradc integer divider control register is 8-bits width.
> 
> Signed-off-by: David Wu <david.wu at rock-chips.com>
> ---
>  arch/arm/include/asm/arch-rockchip/cru_rk3368.h |  5 ++++
>  drivers/clk/rockchip/clk_rk3368.c               | 32 +++++++++++++++++++++++++
>  2 files changed, 37 insertions(+)
> 

Acked-by: Philipp Tomsich <philipp.tomsich at theobroma-systems.com>