[U-Boot] [PATCH] FSL PCI: Configure PCIe reference ratio

[Mingkai Hu]

> -----Original Message-----
> From: York Sun
> Sent: Friday, September 15, 2017 5:15 AM
> To: Joakim Tjernlund <joakim.tjernlund at infinera.com>; Mingkai Hu
> <mingkai.hu at nxp.com>; u-boot @ lists . denx . de <u-boot at lists.denx.de>;
> Roy Zang <roy.zang at nxp.com>
> Subject: Re: [PATCH] FSL PCI: Configure PCIe reference ratio
> 
> On 09/12/2017 10:56 AM, Joakim Tjernlund wrote:
> > Most FSL PCIe controllers expects 333 MHz PCI reference clock.
> > This clock is derived from the CCB but in many cases the ref.
> > clock is not 333 MHz and a divisor needs to be configured.
> >
> > This adds PEX_CCB_DIV #define which can be defined for each type of
> > CPU/platform.
> >
> > Signed-off-by: Joakim Tjernlund <joakim.tjernlund at infinera.com>
> > ---
> >   drivers/pci/fsl_pci_init.c | 6 ++++++
> >   1 file changed, 6 insertions(+)
> >
> > diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
> > index 52792dcd59..4d00b3f26c 100644
> > --- a/drivers/pci/fsl_pci_init.c
> > +++ b/drivers/pci/fsl_pci_init.c
> > @@ -322,6 +322,12 @@ void fsl_pci_init(struct pci_controller *hose,
> > struct fsl_pci_info *pci_info)
> >
> >   	pci_setup_indirect(hose, cfg_addr, cfg_data);
> >
> > +#ifdef PEX_CCB_DIV
> > +	/* Configure the PCIE controller core clock ratio */
> > +	pci_hose_write_config_dword(hose, dev, 0x440,
> > +				    ((gd->bus_clk / 1000000) *
> > +				     (16 / PEX_CCB_DIV)) / 333);
> > +#endif
> >   	block_rev = in_be32(&pci->block_rev1);
> >   	if (PEX_IP_BLK_REV_2_2 <= block_rev) {
> >   		pi = &pci->pit[2];	/* 0xDC0 */
> >
> 
> Mingkai,
> 
> Do you ack this change? This presumes the PCIe clock derives from CCB bus
> clock.
> 

gd->bus_clk indicates the platform clock while PCIe clock could be CCB or CCB/2.
For example, it's CCB/2 for T1040/T1020, CCB for P2020.

I suggest to add the PCIe clock in gd to handle this difference, just like what we've done for other IP clocks.

Thanks,
Mingkai