[U-Boot] [U-Boot, v2, 05/14] clk: rockchip: Add rk3328 SARADC clock support

[David Wu]

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Content preview:  The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
   SARADC integer divider control register is 10-bits width. Signed-off-by:
  David Wu <david.wu at rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich at theobroma-systems.com>
   Reviewed-by: Philipp Tomsich <philipp.tomsich at theobroma-systems.com> ---
  [...] 

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From: David Wu <david.wu at rock-chips.com>
Subject: [U-Boot,v2,05/14] clk: rockchip: Add rk3328 SARADC clock support
Date: Tue, 19 Sep 2017 18:57:10 +0800
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URL: <http://lists.denx.de/pipermail/u-boot/attachments/20170919/8805c05c/attachment.mht>