[U-Boot] [PATCH 01/14] arm: socfpga: stratix10: Add base address map for Statix10 SoC

[See, Chin Liang]

On Tue, 2017-09-19 at 11:51 +0200, Marek Vasut wrote:
> On 09/19/2017 11:22 AM, chin.liang.see at intel.com wrote:
> > 
> > From: Chin Liang See <chin.liang.see at intel.com>
> > 
> > Add the base address map for Statix10 SoC
> > 
> > Signed-off-by: Chin Liang See <chin.liang.see at intel.com>
> Add only the stuff which is not obtainable from DT please.
> 

Sure, let me remove the SDMMC, EMAC and QSPI since they are extracted
from DT today

Thanks
Chin Liang

> > 
> > ---
> >  arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 58
> > ++++++++++++++++++++++
> >  1 file changed, 58 insertions(+)
> >  create mode 100644 arch/arm/mach-
> > socfpga/include/mach/base_addr_s10.h
> > 
> > diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> > b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> > new file mode 100644
> > index 0000000..feb1881
> > --- /dev/null
> > +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> > @@ -0,0 +1,58 @@
> > +/*
> > + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
> > + *
> > + * SPDX-License-Identifier:	GPL-2.0
> > + */
> > +
> > +#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
> > +#define _SOCFPGA_S10_BASE_HARDWARE_H_
> > +
> > +#define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xf8000400
> > +#define SOCFPGA_HMC_MMR_IO48_ADDRESS		0xf8010000
> > +#define SOCFPGA_SDR_ADDRESS			0xf8011000
> > +#define SOCFPGA_SMMU_ADDRESS			0xfa000000
> > +#define SOCFPGA_EMAC0_ADDRESS			0xff800000
> > +#define SOCFPGA_EMAC1_ADDRESS			0xff802000
> > +#define SOCFPGA_EMAC2_ADDRESS			0xff804000
> > +#define SOCFPGA_SDMMC_ADDRESS			0xff808000
> > +#define SOCFPGA_QSPIREGS_ADDRESS		0xff8d2000
> > +#define SOCFPGA_QSPIDATA_ADDRESS		0xff900000
> > +#define SOCFPGA_MAILBOX_ADDRESS			0xffA30000
> > +#define SOCFPGA_USB0_ADDRESS			0xffb00000
> > +#define SOCFPGA_USB1_ADDRESS			0xffb40000
> > +#define SOCFPGA_NANDREGS_ADDRESS		0xffb80000
> > +#define SOCFPGA_NANDDATA_ADDRESS		0xffb90000
> > +#define SOCFPGA_UART0_ADDRESS			0xffc02000
> > +#define SOCFPGA_UART1_ADDRESS			0xffc02100
> > +#define SOCFPGA_I2C0_ADDRESS			0xffc02800
> > +#define SOCFPGA_I2C1_ADDRESS			0xffc02900
> > +#define SOCFPGA_I2C2_ADDRESS			0xffc02a00
> > +#define SOCFPGA_I2C3_ADDRESS			0xffc02b00
> > +#define SOCFPGA_I2C4_ADDRESS			0xffc02c00
> > +#define SOCFPGA_SPTIMER0_ADDRESS		0xffc03000
> > +#define SOCFPGA_SPTIMER1_ADDRESS		0xffc03100
> > +#define SOCFPGA_GPIO0_ADDRESS			0xffc03200
> > +#define SOCFPGA_GPIO1_ADDRESS			0xffc03300
> > +#define SOCFPGA_SYSTIMER0_ADDRESS		0xffd00000
> > +#define SOCFPGA_SYSTIMER1_ADDRESS		0xffd00100
> > +#define SOCFPGA_L4WD0_ADDRESS			0xffd00200
> > +#define SOCFPGA_L4WD1_ADDRESS			0xffd00300
> > +#define SOCFPGA_L4WD2_ADDRESS			0xffd00400
> > +#define SOCFPGA_L4WD3_ADDRESS			0xffd00500
> > +#define SOCFPGA_GTIMER_SEC_ADDRESS		0xffd01000
> > +#define SOCFPGA_GTIMER_NSEC_ADDRESS		0xffd02000
> > +#define SOCFPGA_CLKMGR_ADDRESS			0xffd10000
> > +#define SOCFPGA_RSTMGR_ADDRESS			0xffd11000
> > +#define SOCFPGA_SYSMGR_ADDRESS			0xffd12000
> > +#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS	0xffd13000
> > +#define SOCFPGA_DMANONSECURE_ADDRESS		0xffda0000
> > +#define SOCFPGA_DMASECURE_ADDRESS		0xffda1000
> > +#define SOCFPGA_SPIS0_ADDRESS			0xffda2000
> > +#define SOCFPGA_SPIS1_ADDRESS			0xffda3000
> > +#define SOCFPGA_SPIM0_ADDRESS			0xffda4000
> > +#define SOCFPGA_SPIM1_ADDRESS			0xffda5000
> > +#define SOCFPGA_OCRAM_ADDRESS			0xffe00000
> > +#define GICD_BASE				0xfffc1000
> > +#define GICC_BASE				0xfffc2000
> > +
> > +#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
> > 
>