[U-Boot] [U-Boot, v3, 04/14] rockchip: clk: Add SARADC clock support for rk3288

[Philipp Tomsich]

> The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
> SARADC integer divider control register is 8-bits width.
> 
> Signed-off-by: David Wu <david.wu at rock-chips.com>
> Reviewed-by: Philipp Tomsich <philipp.tomsich at theobroma-systems.com>
> Acked-by: Philipp Tomsich <philipp.tomsich at theobroma-systems.com>
> ---
> 
> Changes in v3: None
> Changes in v2:
> - Use bitfield_extract
> - Use GENMASK
> 
>  drivers/clk/rockchip/clk_rk3288.c | 41 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 41 insertions(+)
> 

Applied to u-boot-rockchip, thanks!