[U-Boot] tegra: fdt: create initial files and changes to support the tegra124 based nyan-kitty chromebase by acer
Benjamin Roszak
benjamin545 at gmail.com
Mon Sep 25 05:42:44 UTC 2017
The intent of this patch is to create the initial files necessary to
support the nyan-kitty device by copying nyan-big files and renaming all
the nyan-big references and tags to be nyan-kitty.
This will make a u-boot that will act exactly like the nyan-big build,
except will say "nyan-kitty" where applicable. the problem with this is
that nyan-kitty doesn't have a uart header on the board and the activated
serial port will cause garbage input to u-boot and cause it to crash.
I have done further work to disable the uart, but this will cause a build
that locks up before display since the input, output, error ,macro will
specify a serial device to use that doesn't exist. This requires some
reworking of the macro to get it to work without a serial device. also
since there is no keyboard built in to the device, usb keyboard needs to be
enabled to allow input. I do not include these changes mentioned in this
paragraph in these patches.
+++
/home/ben/tegra/uboot/new/u-boot-initial/arch/arm/dts/tegra124-nyan-kitty.dts
2017-08-22 23:24:27.864516000 -0400
+/dts-v1/;
+
+#include "tegra124-nyan.dtsi"
+
+/ {
+ model = "Acer Chromebase DC221HQ";
+ compatible = "google,nyan-kitty", "google,nyan", "nvidia,tegra124";
+
+ aliases {
+ console = &uarta;
+ i2c0 = "/i2c at 7000d000";
+ i2c1 = "/i2c at 7000c000";
+ i2c2 = "/i2c at 7000c400";
+ i2c3 = "/i2c at 7000c500";
+ i2c4 = "/i2c at 7000c700";
+ i2c5 = "/i2c at 7000d100";
+ rtc0 = "/i2c at 7000d000/pmic at 40";
+ rtc1 = "/rtc at 7000e000";
+ mmc0 = "/sdhci at 700b0600";
+ mmc1 = "/sdhci at 700b0400";
+ spi0 = "/spi at 7000d400";
+ spi1 = "/spi at 7000da00";
+ usb0 = "/usb at 7d000000";
+ usb1 = "/usb at 7d008000";
+ usb2 = "/usb at 7d004000";
+ };
+
+ chosen {
+ stdout-path = &uarta;
+ };
+
+ host1x at 50000000 {
+ dc at 54200000 {
+ display-timings {
+ timing at 0 {
+ clock-frequency = <69500000>;
+ hactive = <1366>;
+ vactive = <768>;
+ hsync-len = <32>;
+ hfront-porch = <48>;
+ hback-porch = <20>;
+ vfront-porch = <3>;
+ vback-porch = <13>;
+ vsync-len = <6>;
+ };
+ };
+ };
+
+ dc at 54240000 {
+ status = "disabled";
+ };
+
+ };
+
+ panel: panel {
+ compatible = "auo,b133xtn01";
+
+ backlight = <&backlight>;
+ ddc-i2c-bus = <&dpaux>;
+ };
+
+ sdhci at 700b0400 { /* SD Card on this bus */
+ wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
+ };
+
+ sound {
+ compatible = "nvidia,tegra-audio-max98090-nyan-kitty",
+ "nvidia,tegra-audio-max98090-nyan",
+ "nvidia,tegra-audio-max98090";
+ nvidia,model = "GoogleNyanKitty";
+ };
+
+
+ pinmux at 70000868 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinmux_default>;
+
+ pinmux_default: common {
+ clk_32k_out_pa0 {
+ nvidia,pins = "clk_32k_out_pa0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uart3_cts_n_pa1 {
+ nvidia,pins = "uart3_cts_n_pa1";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap2_fs_pa2 {
+ nvidia,pins = "dap2_fs_pa2";
+ nvidia,function = "i2s1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap2_sclk_pa3 {
+ nvidia,pins = "dap2_sclk_pa3";
+ nvidia,function = "i2s1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap2_din_pa4 {
+ nvidia,pins = "dap2_din_pa4";
+ nvidia,function = "i2s1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap2_dout_pa5 {
+ nvidia,pins = "dap2_dout_pa5";
+ nvidia,function = "i2s1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_clk_pa6 {
+ nvidia,pins = "sdmmc3_clk_pa6";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ sdmmc3_cmd_pa7 {
+ nvidia,pins = "sdmmc3_cmd_pa7";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pb0 {
+ nvidia,pins = "pb0";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pb1 {
+ nvidia,pins = "pb1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ sdmmc3_dat3_pb4 {
+ nvidia,pins = "sdmmc3_dat3_pb4";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_dat2_pb5 {
+ nvidia,pins = "sdmmc3_dat2_pb5";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_dat1_pb6 {
+ nvidia,pins = "sdmmc3_dat1_pb6";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_dat0_pb7 {
+ nvidia,pins = "sdmmc3_dat0_pb7";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uart3_rts_n_pc0 {
+ nvidia,pins = "uart3_rts_n_pc0";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uart2_txd_pc2 {
+ nvidia,pins = "uart2_txd_pc2";
+ nvidia,function = "irda";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uart2_rxd_pc3 {
+ nvidia,pins = "uart2_rxd_pc3";
+ nvidia,function = "irda";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gen1_i2c_scl_pc4 {
+ nvidia,pins = "gen1_i2c_scl_pc4";
+ nvidia,function = "i2c1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ gen1_i2c_sda_pc5 {
+ nvidia,pins = "gen1_i2c_sda_pc5";
+ nvidia,function = "i2c1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ pc7 {
+ nvidia,pins = "pc7";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pg0 {
+ nvidia,pins = "pg0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pg1 {
+ nvidia,pins = "pg1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pg2 {
+ nvidia,pins = "pg2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pg3 {
+ nvidia,pins = "pg3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pg4 {
+ nvidia,pins = "pg4";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pg5 {
+ nvidia,pins = "pg5";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pg6 {
+ nvidia,pins = "pg6";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pg7 {
+ nvidia,pins = "pg7";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ph0 {
+ nvidia,pins = "ph0";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ph1 {
+ nvidia,pins = "ph1";
+ nvidia,function = "pwm1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ph2 {
+ nvidia,pins = "ph2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ph3 {
+ nvidia,pins = "ph3";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ph4 {
+ nvidia,pins = "ph4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ph5 {
+ nvidia,pins = "ph5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ph6 {
+ nvidia,pins = "ph6";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ph7 {
+ nvidia,pins = "ph7";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pi0 {
+ nvidia,pins = "pi0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pi1 {
+ nvidia,pins = "pi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pi2 {
+ nvidia,pins = "pi2";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pi3 {
+ nvidia,pins = "pi3";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pi4 {
+ nvidia,pins = "pi4";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ soc_warm_reset_l {
+ nvidia,pins = "pi5";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pi6 {
+ nvidia,pins = "pi6";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ hp_det_l {
+ nvidia,pins = "pi7";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pj0 {
+ nvidia,pins = "pj0";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pj2 {
+ nvidia,pins = "pj2";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uart2_cts_n_pj5 {
+ nvidia,pins = "uart2_cts_n_pj5";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uart2_rts_n_pj6 {
+ nvidia,pins = "uart2_rts_n_pj6";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pj7 {
+ nvidia,pins = "pj7";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pk0 {
+ nvidia,pins = "pk0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pk1 {
+ nvidia,pins = "pk1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pk2 {
+ nvidia,pins = "pk2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pk3 {
+ nvidia,pins = "pk3";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pk4 {
+ nvidia,pins = "pk4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spdif_out_pk5 {
+ nvidia,pins = "spdif_out_pk5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spdif_in_pk6 {
+ nvidia,pins = "spdif_in_pk6";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pk7 {
+ nvidia,pins = "pk7";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap1_fs_pn0 {
+ nvidia,pins = "dap1_fs_pn0";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap1_din_pn1 {
+ nvidia,pins = "dap1_din_pn1";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap1_dout_pn2 {
+ nvidia,pins = "dap1_dout_pn2";
+ nvidia,function = "i2s0";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap1_sclk_pn3 {
+ nvidia,pins = "dap1_sclk_pn3";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ usb_vbus_en0_pn4 {
+ nvidia,pins = "usb_vbus_en0_pn4";
+ nvidia,function = "usb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ usb_vbus_en1_pn5 {
+ nvidia,pins = "usb_vbus_en1_pn5";
+ nvidia,function = "usb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ hdmi_int_pn7 {
+ nvidia,pins = "hdmi_int_pn7";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_data7_po0 {
+ nvidia,pins = "ulpi_data7_po0";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_data0_po1 {
+ nvidia,pins = "ulpi_data0_po1";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_data1_po2 {
+ nvidia,pins = "ulpi_data1_po2";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_data2_po3 {
+ nvidia,pins = "ulpi_data2_po3";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_data3_po4 {
+ nvidia,pins = "ulpi_data3_po4";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_data4_po5 {
+ nvidia,pins = "ulpi_data4_po5";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_data5_po6 {
+ nvidia,pins = "ulpi_data5_po6";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_data6_po7 {
+ nvidia,pins = "ulpi_data6_po7";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap3_fs_pp0 {
+ nvidia,pins = "dap3_fs_pp0";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap3_din_pp1 {
+ nvidia,pins = "dap3_din_pp1";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap3_dout_pp2 {
+ nvidia,pins = "dap3_dout_pp2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap3_sclk_pp3 {
+ nvidia,pins = "dap3_sclk_pp3";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap4_fs_pp4 {
+ nvidia,pins = "dap4_fs_pp4";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap4_din_pp5 {
+ nvidia,pins = "dap4_din_pp5";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap4_dout_pp6 {
+ nvidia,pins = "dap4_dout_pp6";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap4_sclk_pp7 {
+ nvidia,pins = "dap4_sclk_pp7";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_col0_pq0 {
+ nvidia,pins = "kb_col0_pq0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_col1_pq1 {
+ nvidia,pins = "kb_col1_pq1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_col2_pq2 {
+ nvidia,pins = "kb_col2_pq2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_col3_pq3 {
+ nvidia,pins = "kb_col3_pq3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_col4_pq4 {
+ nvidia,pins = "kb_col4_pq4";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_col5_pq5 {
+ nvidia,pins = "kb_col5_pq5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_col6_pq6 {
+ nvidia,pins = "kb_col6_pq6";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_col7_pq7 {
+ nvidia,pins = "kb_col7_pq7";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_row0_pr0 {
+ nvidia,pins = "kb_row0_pr0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row1_pr1 {
+ nvidia,pins = "kb_row1_pr1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_row2_pr2 {
+ nvidia,pins = "kb_row2_pr2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row3_pr3 {
+ nvidia,pins = "kb_row3_pr3";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row4_pr4 {
+ nvidia,pins = "kb_row4_pr4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_row5_pr5 {
+ nvidia,pins = "kb_row5_pr5";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row6_pr6 {
+ nvidia,pins = "kb_row6_pr6";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row7_pr7 {
+ nvidia,pins = "kb_row7_pr7";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_row8_ps0 {
+ nvidia,pins = "kb_row8_ps0";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row9_ps1 {
+ nvidia,pins = "kb_row9_ps1";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row10_ps2 {
+ nvidia,pins = "kb_row10_ps2";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_row11_ps3 {
+ nvidia,pins = "kb_row11_ps3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row12_ps4 {
+ nvidia,pins = "kb_row12_ps4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row13_ps5 {
+ nvidia,pins = "kb_row13_ps5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row14_ps6 {
+ nvidia,pins = "kb_row14_ps6";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row15_ps7 {
+ nvidia,pins = "kb_row15_ps7";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_row16_pt0 {
+ nvidia,pins = "kb_row16_pt0";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row17_pt1 {
+ nvidia,pins = "kb_row17_pt1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gen2_i2c_scl_pt5 {
+ nvidia,pins = "gen2_i2c_scl_pt5";
+ nvidia,function = "i2c2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ gen2_i2c_sda_pt6 {
+ nvidia,pins = "gen2_i2c_sda_pt6";
+ nvidia,function = "i2c2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_cmd_pt7 {
+ nvidia,pins = "sdmmc4_cmd_pt7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pu0 {
+ nvidia,pins = "pu0";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pu1 {
+ nvidia,pins = "pu1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pu2 {
+ nvidia,pins = "pu2";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pu3 {
+ nvidia,pins = "pu3";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pu4 {
+ nvidia,pins = "pu4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pu5 {
+ nvidia,pins = "pu5";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ bt_irq {
+ nvidia,pins = "pu6";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pv0 {
+ nvidia,pins = "pv0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pv1 {
+ nvidia,pins = "pv1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ sdmmc3_cd_n_pv2 {
+ nvidia,pins = "sdmmc3_cd_n_pv2";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_wp_n_pv3 {
+ nvidia,pins = "sdmmc1_wp_n_pv3";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ddc_scl_pv4 {
+ nvidia,pins = "ddc_scl_pv4";
+ nvidia,function = "i2c4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+ };
+ ddc_sda_pv5 {
+ nvidia,pins = "ddc_sda_pv5";
+ nvidia,function = "i2c4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+ };
+ gpio_w2_aud_pw2 {
+ nvidia,pins = "gpio_w2_aud_pw2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gpio_w3_aud_pw3 {
+ nvidia,pins = "gpio_w3_aud_pw3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap_mclk1_pw4 {
+ nvidia,pins = "dap_mclk1_pw4";
+ nvidia,function = "extperiph1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ clk2_out_pw5 {
+ nvidia,pins = "clk2_out_pw5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uart3_txd_pw6 {
+ nvidia,pins = "uart3_txd_pw6";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uart3_rxd_pw7 {
+ nvidia,pins = "uart3_rxd_pw7";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dvfs_pwm_px0 {
+ nvidia,pins = "dvfs_pwm_px0";
+ nvidia,function = "cldvfs";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gpio_x1_aud_px1 {
+ nvidia,pins = "gpio_x1_aud_px1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dvfs_clk_px2 {
+ nvidia,pins = "dvfs_clk_px2";
+ nvidia,function = "cldvfs";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gpio_x3_aud_px3 {
+ nvidia,pins = "gpio_x3_aud_px3";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gpio_x4_aud_px4 {
+ nvidia,pins = "gpio_x4_aud_px4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gpio_x5_aud_px5 {
+ nvidia,pins = "gpio_x5_aud_px5";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gpio_x6_aud_px6 {
+ nvidia,pins = "gpio_x6_aud_px6";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gpio_x7_aud_px7 {
+ nvidia,pins = "gpio_x7_aud_px7";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_clk_py0 {
+ nvidia,pins = "ulpi_clk_py0";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_dir_py1 {
+ nvidia,pins = "ulpi_dir_py1";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi_nxt_py2 {
+ nvidia,pins = "ulpi_nxt_py2";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_stp_py3 {
+ nvidia,pins = "ulpi_stp_py3";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ sdmmc1_dat3_py4 {
+ nvidia,pins = "sdmmc1_dat3_py4";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_dat2_py5 {
+ nvidia,pins = "sdmmc1_dat2_py5";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_dat1_py6 {
+ nvidia,pins = "sdmmc1_dat1_py6";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_dat0_py7 {
+ nvidia,pins = "sdmmc1_dat0_py7";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_clk_pz0 {
+ nvidia,pins = "sdmmc1_clk_pz0";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_cmd_pz1 {
+ nvidia,pins = "sdmmc1_cmd_pz1";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pwr_i2c_scl_pz6 {
+ nvidia,pins = "pwr_i2c_scl_pz6";
+ nvidia,function = "i2cpwr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ pwr_i2c_sda_pz7 {
+ nvidia,pins = "pwr_i2c_sda_pz7";
+ nvidia,function = "i2cpwr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_dat0_paa0 {
+ nvidia,pins = "sdmmc4_dat0_paa0";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_dat1_paa1 {
+ nvidia,pins = "sdmmc4_dat1_paa1";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_dat2_paa2 {
+ nvidia,pins = "sdmmc4_dat2_paa2";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_dat3_paa3 {
+ nvidia,pins = "sdmmc4_dat3_paa3";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_dat4_paa4 {
+ nvidia,pins = "sdmmc4_dat4_paa4";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_dat5_paa5 {
+ nvidia,pins = "sdmmc4_dat5_paa5";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_dat6_paa6 {
+ nvidia,pins = "sdmmc4_dat6_paa6";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_dat7_paa7 {
+ nvidia,pins = "sdmmc4_dat7_paa7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb0 {
+ nvidia,pins = "pbb0";
+ nvidia,function = "vgp6";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ cam_i2c_scl_pbb1 {
+ nvidia,pins = "cam_i2c_scl_pbb1";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ };
+ cam_i2c_sda_pbb2 {
+ nvidia,pins = "cam_i2c_sda_pbb2";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ };
+ pbb3 {
+ nvidia,pins = "pbb3";
+ nvidia,function = "vgp3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pbb4 {
+ nvidia,pins = "pbb4";
+ nvidia,function = "vgp4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pbb5 {
+ nvidia,pins = "pbb5";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pbb6 {
+ nvidia,pins = "pbb6";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pbb7 {
+ nvidia,pins = "pbb7";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ cam_mclk_pcc0 {
+ nvidia,pins = "cam_mclk_pcc0";
+ nvidia,function = "vi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pcc1 {
+ nvidia,pins = "pcc1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pcc2 {
+ nvidia,pins = "pcc2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ sdmmc4_clk_pcc4 {
+ nvidia,pins = "sdmmc4_clk_pcc4";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk2_req_pcc5 {
+ nvidia,pins = "clk2_req_pcc5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pex_l0_rst_n_pdd1 {
+ nvidia,pins = "pex_l0_rst_n_pdd1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pex_l0_clkreq_n_pdd2 {
+ nvidia,pins = "pex_l0_clkreq_n_pdd2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pex_wake_n_pdd3 {
+ nvidia,pins = "pex_wake_n_pdd3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pex_l1_rst_n_pdd5 {
+ nvidia,pins = "pex_l1_rst_n_pdd5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pex_l1_clkreq_n_pdd6 {
+ nvidia,pins = "pex_l1_clkreq_n_pdd6";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ clk3_out_pee0 {
+ nvidia,pins = "clk3_out_pee0";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ clk3_req_pee1 {
+ nvidia,pins = "clk3_req_pee1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap_mclk1_req_pee2 {
+ nvidia,pins = "dap_mclk1_req_pee2";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ hdmi_cec_pee3 {
+ nvidia,pins = "hdmi_cec_pee3";
+ nvidia,function = "cec";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_clk_lb_out_pee4 {
+ nvidia,pins = "sdmmc3_clk_lb_out_pee4";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ sdmmc3_clk_lb_in_pee5 {
+ nvidia,pins = "sdmmc3_clk_lb_in_pee5";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dp_hpd_pff0 {
+ nvidia,pins = "dp_hpd_pff0";
+ nvidia,function = "dp";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ usb_vbus_en2_pff1 {
+ nvidia,pins = "usb_vbus_en2_pff1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ };
+ pff2 {
+ nvidia,pins = "pff2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ };
+ core_pwr_req {
+ nvidia,pins = "core_pwr_req";
+ nvidia,function = "pwron";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ cpu_pwr_req {
+ nvidia,pins = "cpu_pwr_req";
+ nvidia,function = "cpu";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pwr_int_n {
+ nvidia,pins = "pwr_int_n";
+ nvidia,function = "pmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ reset_out_n {
+ nvidia,pins = "reset_out_n";
+ nvidia,function = "reset_out_n";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ owr {
+ nvidia,pins = "owr";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+ };
+ clk_32k_in {
+ nvidia,pins = "clk_32k_in";
+ nvidia,function = "clk";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ jtag_rtck {
+ nvidia,pins = "jtag_rtck";
+ nvidia,function = "rtck";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ };
+ };
+
+
+
+
+
+};
+++
/home/ben/tegra/uboot/new/u-boot-initial/arch/arm/dts/tegra124-nyan-kitty-u-boot.dtsi
2017-08-22 23:27:09.230719000 -0400
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <sjg at chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/ {
+ host1x at 50000000 {
+ u-boot,dm-pre-reloc;
+ dc at 54200000 {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ spi at 7000d400 {
+ spi-deactivate-delay = <200>;
+ spi-max-frequency = <3000000>;
+
+ cros_ec: cros-ec at 0 {
+ ec-interrupt = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+++
/home/ben/tegra/uboot/new/u-boot-initial/arch/arm/mach-tegra/tegra124/Kconfig
2017-08-21 00:33:15.626545000 -0400
+config TARGET_NYAN_KITTY
+ bool "Google/NVIDIA Nyan-kitty Chromebase"
+ select BOARD_LATE_INIT
+ help
+ Nyan Kitty is a Tegra124 All in one Desktop computer "Chromebase"
+ that is very similar to the Acer 13 Chromebook.
+ Some versions may have a touchscreen, all versions should have a
+ 22 inch LCD screen, 2 speakers, webcam with mic, HDMI out port,
+ 2 USB 2.0 and 1 USB 3.0 port, full size SD card slot, headphone out,
+ and 10/100 Ethernet (USB). There is 4GB of ram and 16GB of MMC
storage.
+ The retail name is the Acer Chromebase HD221HQ
+
+source "board/nvidia/nyan-kitty/Kconfig"
+++
/home/ben/tegra/uboot/new/u-boot-initial/board/nvidia/nyan-kitty/Kconfig
2017-08-17 21:15:42.848925000 -0400
+if TARGET_NYAN_KITTY
+
+config SYS_BOARD
+ default "nyan-kitty"
+
+config SYS_VENDOR
+ default "nvidia"
+
+config SYS_CONFIG_NAME
+ default "nyan-kitty"
+
+endif
+++
/home/ben/tegra/uboot/new/u-boot-initial/board/nvidia/nyan-kitty/MAINTAINERS
2017-08-17 21:24:08.016664000 -0400
+NYAN-KITTY BOARD
+M:
+S: Maintained
+F: board/nvidia/nyan-kitty/
+F: include/configs/nyan-kitty.h
+F: configs/nyan-kitty_defconfig
+++
/home/ben/tegra/uboot/new/u-boot-initial/board/nvidia/nyan-kitty/Makefile
2017-08-17 21:16:33.744523000 -0400
+#
+# (C) Copyright 2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ../venice2/as3722_init.o
+obj-y += nyan-kitty.o
+++
/home/ben/tegra/uboot/new/u-boot-initial/board/nvidia/nyan-kitty/nyan-kitty.c
2017-08-17 21:32:14.656228000 -0400
+/*
+ * (C) Copyright 2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mc.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <power/as3722.h>
+#include <power/pmic.h>
+#include "pinmux-config-nyan-kitty.h"
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+ gpio_config_table(nyan_kitty_gpio_inits,
+ ARRAY_SIZE(nyan_kitty_gpio_inits));
+
+ pinmux_config_pingrp_table(nyan_kitty_pingrps,
+ ARRAY_SIZE(nyan_kitty_pingrps));
+
+ pinmux_config_drvgrp_table(nyan_kitty_drvgrps,
+ ARRAY_SIZE(nyan_kitty_drvgrps));
+}
+
+int tegra_board_id(void)
+{
+ static const int vector[] = {TEGRA_GPIO(Q, 3), TEGRA_GPIO(T, 1),
+ TEGRA_GPIO(X, 1), TEGRA_GPIO(X, 4),
+ -1};
+
+ gpio_claim_vector(vector, "board_id%d");
+ return gpio_get_values_as_int(vector);
+}
+
+int tegra_lcd_pmic_init(int board_id)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_PMIC,
+ DM_GET_DRIVER(pmic_as3722), &dev);
+ if (ret) {
+ debug("%s: Failed to find PMIC\n", __func__);
+ return ret;
+ }
+
+ if (board_id == 0)
+ pmic_reg_write(dev, 0x00, 0x3c);
+ else
+ pmic_reg_write(dev, 0x00, 0x50);
+ pmic_reg_write(dev, 0x12, 0x10);
+ pmic_reg_write(dev, 0x0c, 0x07);
+ pmic_reg_write(dev, 0x20, 0x10);
+
+ return 0;
+}
+
+/* Setup required information for Linux kernel */
+static void setup_kernel_info(void)
+{
+ struct mc_ctlr *mc = (void *)NV_PA_MC_BASE;
+
+ /* The kernel graphics driver needs this region locked down */
+ writel(0, &mc->mc_video_protect_bom);
+ writel(0, &mc->mc_video_protect_size_mb);
+ writel(1, &mc->mc_video_protect_reg_ctrl);
+}
+
+/*
+ * We need to take ALL audio devices conntected to AHUB (AUDIO, APBIF,
+ * I2S, DAM, AMX, ADX, SPDIF, AFC) out of reset and enable the clocks.
+ * Otherwise reading AHUB devices will hang when the kernel boots.
+ */
+static void enable_required_clocks(void)
+{
+ static enum periph_id ids[] = {
+ PERIPH_ID_I2S0,
+ PERIPH_ID_I2S1,
+ PERIPH_ID_I2S2,
+ PERIPH_ID_I2S3,
+ PERIPH_ID_I2S4,
+ PERIPH_ID_AUDIO,
+ PERIPH_ID_APBIF,
+ PERIPH_ID_DAM0,
+ PERIPH_ID_DAM1,
+ PERIPH_ID_DAM2,
+ PERIPH_ID_AMX0,
+ PERIPH_ID_AMX1,
+ PERIPH_ID_ADX0,
+ PERIPH_ID_ADX1,
+ PERIPH_ID_SPDIF,
+ PERIPH_ID_AFC0,
+ PERIPH_ID_AFC1,
+ PERIPH_ID_AFC2,
+ PERIPH_ID_AFC3,
+ PERIPH_ID_AFC4,
+ PERIPH_ID_AFC5,
+ PERIPH_ID_EXTPERIPH1
+ };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ids); i++)
+ clock_enable(ids[i]);
+ udelay(2);
+ for (i = 0; i < ARRAY_SIZE(ids); i++)
+ reset_set_enable(ids[i], 0);
+}
+
+int nvidia_board_init(void)
+{
+ clock_start_periph_pll(PERIPH_ID_EXTPERIPH1, CLOCK_ID_OSC, 12000000);
+ clock_start_periph_pll(PERIPH_ID_I2S1, CLOCK_ID_OSC, 1500000);
+
+ /* For external MAX98090 audio codec */
+ clock_external_output(1);
+ setup_kernel_info();
+ enable_required_clocks();
+
+ return 0;
+}
+++
/home/ben/tegra/uboot/new/u-boot-initial/board/nvidia/nyan-kitty/pinmux-config-nyan-kitty.h
2017-08-17 21:28:54.494075000 -0400
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
+ *
+ * To generate this file, use the tegra-pinmux-scripts tool available from
+ * https://github.com/NVIDIA/tegra-pinmux-scripts
+ * Run "board-to-uboot.py nyan-big".
+ */
+
+#ifndef _PINMUX_CONFIG_NYAN_KITTY_H_
+#define _PINMUX_CONFIG_NYAN_KITTY_H_
+
+#define GPIO_INIT(_port, _gpio, _init) \
+ { \
+ .gpio = TEGRA_GPIO(_port, _gpio), \
+ .init = TEGRA_GPIO_INIT_##_init, \
+ }
+
+static const struct tegra_gpio_config nyan_kitty_gpio_inits[] = {
+ /* port, pin, init_val */
+ GPIO_INIT(A, 0, IN),
+ GPIO_INIT(C, 7, IN),
+ GPIO_INIT(G, 0, IN),
+ GPIO_INIT(G, 1, IN),
+ GPIO_INIT(G, 2, IN),
+ GPIO_INIT(G, 3, IN),
+ GPIO_INIT(H, 2, IN),
+ GPIO_INIT(H, 4, IN),
+ GPIO_INIT(H, 6, IN),
+ GPIO_INIT(H, 7, OUT1),
+ GPIO_INIT(I, 0, IN),
+ GPIO_INIT(I, 1, IN),
+ GPIO_INIT(I, 5, OUT1),
+ GPIO_INIT(I, 6, IN),
+ GPIO_INIT(I, 7, IN),
+ GPIO_INIT(J, 0, IN),
+ GPIO_INIT(J, 7, IN),
+ GPIO_INIT(K, 1, OUT0),
+ GPIO_INIT(K, 2, IN),
+ GPIO_INIT(K, 4, OUT0),
+ GPIO_INIT(K, 6, OUT0),
+ GPIO_INIT(K, 7, IN),
+ GPIO_INIT(N, 7, IN),
+ GPIO_INIT(P, 2, OUT0),
+ GPIO_INIT(Q, 0, IN),
+ GPIO_INIT(Q, 2, IN),
+ GPIO_INIT(Q, 3, IN),
+ GPIO_INIT(Q, 6, IN),
+ GPIO_INIT(Q, 7, IN),
+ GPIO_INIT(R, 0, OUT0),
+ GPIO_INIT(R, 1, IN),
+ GPIO_INIT(R, 4, IN),
+ GPIO_INIT(R, 7, IN),
+ GPIO_INIT(S, 3, OUT0),
+ GPIO_INIT(S, 4, OUT0),
+ GPIO_INIT(S, 7, IN),
+ GPIO_INIT(T, 1, IN),
+ GPIO_INIT(U, 4, IN),
+ GPIO_INIT(U, 5, IN),
+ GPIO_INIT(U, 6, IN),
+ GPIO_INIT(V, 0, IN),
+ GPIO_INIT(W, 3, IN),
+ GPIO_INIT(X, 1, IN),
+ GPIO_INIT(X, 4, IN),
+ GPIO_INIT(X, 7, OUT0),
+};
+
+#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .od = PMUX_PIN_OD_##_od, \
+ .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \
+ .lock = PMUX_PIN_LOCK_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+static const struct pmux_pingrp_config nyan_kitty_pingrps[] = {
+ /* pingrp, mux, pull, tri, e_input,
od, rcv_sel */
+ PINCFG(CLK_32K_OUT_PA0, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(UART3_CTS_N_PA1, GMI, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(PB0, RSVD2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PB1, RSVD2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(UART3_RTS_N_PC0, GMI, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(UART2_TXD_PC2, IRDA, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(UART2_RXD_PC3, IRDA, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT,
ENABLE, DEFAULT),
+ PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT,
ENABLE, DEFAULT),
+ PINCFG(PC7, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(PG0, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(PG1, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(PG2, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(PG3, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(PH0, GMI, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PH2, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(PH3, GMI, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PH4, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(PH5, RSVD2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PH6, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(PH7, DEFAULT, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PI0, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(PI1, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(PI2, RSVD4, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PI4, GMI, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PI5, DEFAULT, UP, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PI6, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(PI7, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(PJ0, DEFAULT, UP, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(PJ2, RSVD1, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(UART2_CTS_N_PJ5, GMI, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(UART2_RTS_N_PJ6, GMI, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PJ7, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(PK0, RSVD1, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PK2, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(PK3, GMI, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PK4, DEFAULT, UP, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(SPDIF_OUT_PK5, RSVD2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(SPDIF_IN_PK6, DEFAULT, DOWN, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PK7, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(DAP1_FS_PN0, RSVD4, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(DAP1_DIN_PN1, RSVD4, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(DAP1_DOUT_PN2, I2S0, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(DAP1_SCLK_PN3, RSVD4, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT,
ENABLE, DEFAULT),
+ PINCFG(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT,
ENABLE, DEFAULT),
+ PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, NORMAL, INPUT,
DEFAULT, NORMAL),
+ PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA0_PO1, ULPI, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA1_PO2, ULPI, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA2_PO3, ULPI, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA3_PO4, ULPI, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA4_PO5, ULPI, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA5_PO6, ULPI, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA6_PO7, ULPI, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(DAP3_FS_PP0, I2S2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(DAP3_DIN_PP1, I2S2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(DAP4_FS_PP4, RSVD4, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(DAP4_DIN_PP5, RSVD3, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(DAP4_DOUT_PP6, RSVD4, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(DAP4_SCLK_PP7, RSVD3, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(KB_COL0_PQ0, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(KB_COL1_PQ1, RSVD2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(KB_COL2_PQ2, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(KB_COL3_PQ3, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(KB_COL5_PQ5, RSVD2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(KB_COL6_PQ6, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(KB_COL7_PQ7, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(KB_ROW1_PR1, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(KB_ROW2_PR2, RSVD2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(KB_ROW3_PR3, KBC, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(KB_ROW4_PR4, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(KB_ROW5_PR5, RSVD3, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(KB_ROW6_PR6, KBC, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(KB_ROW7_PR7, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(KB_ROW8_PS0, RSVD2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(KB_ROW9_PS1, UARTA, DOWN, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(KB_ROW10_PS2, UARTA, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(KB_ROW11_PS3, DEFAULT, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(KB_ROW12_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(KB_ROW13_PS5, RSVD2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(KB_ROW14_PS6, RSVD2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(KB_ROW15_PS7, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(KB_ROW16_PT0, RSVD2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT,
ENABLE, DEFAULT),
+ PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT,
ENABLE, DEFAULT),
+ PINCFG(SDMMC4_CMD_PT7, SDMMC4, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(PU0, RSVD4, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PU1, RSVD1, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PU2, RSVD1, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PU3, GMI, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PU4, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(PU5, DEFAULT, UP, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(PU6, DEFAULT, UP, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(PV0, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(PV1, RSVD1, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT,
DEFAULT, NORMAL),
+ PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT,
DEFAULT, NORMAL),
+ PINCFG(GPIO_W2_AUD_PW2, RSVD2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(GPIO_W3_AUD_PW3, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(CLK2_OUT_PW5, RSVD2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(UART3_TXD_PW6, RSVD2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(UART3_RXD_PW7, RSVD2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(GPIO_X3_AUD_PX3, RSVD4, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(GPIO_X5_AUD_PX5, RSVD4, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(GPIO_X6_AUD_PX6, GMI, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(ULPI_DIR_PY1, SPI1, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT,
ENABLE, DEFAULT),
+ PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT,
ENABLE, DEFAULT),
+ PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(PBB0, VGP6, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT,
ENABLE, DEFAULT),
+ PINCFG(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT,
ENABLE, DEFAULT),
+ PINCFG(PBB3, VGP3, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PBB4, VGP4, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PBB5, RSVD3, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PBB6, RSVD2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PBB7, RSVD2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(CAM_MCLK_PCC0, VI, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PCC1, RSVD2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PCC2, RSVD2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(CLK2_REQ_PCC5, RSVD2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PEX_L0_RST_N_PDD1, RSVD2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PEX_L0_CLKREQ_N_PDD2, RSVD2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PEX_WAKE_N_PDD3, RSVD2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PEX_L1_RST_N_PDD5, RSVD2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PEX_L1_CLKREQ_N_PDD6, RSVD2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(CLK3_OUT_PEE0, RSVD2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(CLK3_REQ_PEE1, RSVD2, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(DAP_MCLK1_REQ_PEE2, RSVD4, DOWN, TRISTATE, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT,
ENABLE, DEFAULT),
+ PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(DP_HPD_PFF0, DP, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(USB_VBUS_EN2_PFF1, RSVD2, DOWN, TRISTATE, OUTPUT,
DISABLE, DEFAULT),
+ PINCFG(PFF2, RSVD2, DOWN, TRISTATE, OUTPUT,
DISABLE, DEFAULT),
+ PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PWR_INT_N, PMI, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT,
DEFAULT, NORMAL),
+ PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+};
+
+#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm)
\
+ { \
+ .drvgrp = PMUX_DRVGRP_##_drvgrp, \
+ .slwf = _slwf, \
+ .slwr = _slwr, \
+ .drvup = _drvup, \
+ .drvdn = _drvdn, \
+ .lpmd = PMUX_LPMD_##_lpmd, \
+ .schmt = PMUX_SCHMT_##_schmt, \
+ .hsm = PMUX_HSM_##_hsm, \
+ }
+
+static const struct pmux_drvgrp_config nyan_kitty_drvgrps[] = {
+};
+
+#endif /* PINMUX_CONFIG_NYAN_KITTY_H */
+++
/home/ben/tegra/uboot/new/u-boot-initial/configs/nyan-kitty_defconfig
2017-08-22 23:30:25.553267000 -0400
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA124=y
+CONFIG_TARGET_NYAN_KITTY=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra124-nyan-kitty"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_BEST_MATCH=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTSTAGE=y
+CONFIG_SPL_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_STASH=y
+CONFIG_BOOTSTAGE_STASH_ADDR=0x83000000
+CONFIG_SYS_STDIO_DEREGISTER=y
+CONFIG_SYS_PROMPT="Tegra124 (Nyan-kitty) # "
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_BOOTSTAGE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_TPM=y
+CONFIG_CMD_TPM_TEST=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_LIVE=y
+CONFIG_SPL_DM=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_CROS_EC_KEYB=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_AS3722=y
+CONFIG_DM_REGULATOR=y
+CONFIG_REGULATOR_AS3722=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_PWM_TEGRA=y
+CONFIG_DEBUG_UART_BASE=0x70006000
+CONFIG_DEBUG_UART_CLOCK=408000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_TEGRA114_SPI=y
+CONFIG_TPM_TIS_INFINEON=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="NVIDIA"
+CONFIG_G_DNL_VENDOR_NUM=0x0955
+CONFIG_G_DNL_PRODUCT_NUM=0x701a
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_TEGRA124=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_TPM=y
+CONFIG_ERRNO_STR=y
+++
/home/ben/tegra/uboot/new/u-boot-initial/include/configs/nyan-kitty.h
2017-08-20 20:41:18.593899000 -0400
+/*
+ * (C) Copyright 2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#include "tegra124-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING "Google/NVIDIA Nyan-kitty"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/* I2C */
+#define CONFIG_SYS_I2C_TEGRA
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 2
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
+
+/* Align LCD to 1MB boundary */
+#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
+
+/* SPI */
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED 24000000
+#define CONFIG_SPI_FLASH_SIZE (4 << 20)
+
+/* USB Host support */
+#define CONFIG_USB_EHCI_TEGRA
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+
+#define CONFIG_KEYBOARD
+
+#undef CONFIG_LOADADDR
+#define CONFIG_LOADADDR 0x82408000
+
+#include "tegra-common-usb-gadget.h"
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
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