[U-Boot] [PATCH v2 01/19] ARM: socfpga: add bindings doc for arria10 fpga manager

[Marek Vasut]

On 09/25/2017 10:39 AM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee at intel.com>
> 
> This DT binding doc is porting from Linux DT binding doc.
> commit 1adcbea4201a6852362aa5ece573f1f169b28113
> 
> Add a device tree bindings document for the SoCFPGA Arria10
> FPGA Manager driver.
> 
> Signed-off-by: Alan Tull <atull at opensource.altera.com>
> Acked-by: Rob Herring <robh at kernel.org>
> Acked-By: Moritz Fischer <moritz.fischer at ettus.com>
> Signed-off-by: Rob Herring <robh at kernel.org>
> Signed-off-by: Tien Fong Chee <tien.fong.chee at intel.com>

Applied, thanks

> ---
>  .../fpga/altera-socfpga-a10-fpga-mgr.txt              | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>  create mode 100644 doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
> 
> diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
> new file mode 100644
> index 0000000..2fd8e7a
> --- /dev/null
> +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
> @@ -0,0 +1,19 @@
> +Altera SOCFPGA Arria10 FPGA Manager
> +
> +Required properties:
> +- compatible : should contain "altr,socfpga-a10-fpga-mgr"
> +- reg        : base address and size for memory mapped io.
> +               - The first index is for FPGA manager register access.
> +               - The second index is for writing FPGA configuration data.
> +- resets     : Phandle and reset specifier for the device's reset.
> +- clocks     : Clocks used by the device.
> +
> +Example:
> +
> +	fpga_mgr: fpga-mgr at ffd03000 {
> +		compatible = "altr,socfpga-a10-fpga-mgr";
> +		reg = <0xffd03000 0x100
> +		       0xffcfe400 0x20>;
> +		clocks = <&l4_mp_clk>;
> +		resets = <&rst FPGAMGR_RESET>;
> +	};
> 


-- 
Best regards,
Marek Vasut