[U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA RBF properties at Arria 10 FPGA manager

[Marek Vasut]

On 09/25/2017 10:39 AM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee at intel.com>
> 
> This patch adds description on properties about location of FPGA RBFs are
> stored, type and functionality of RBF used to configure FPGA.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee at intel.com>

Why does this patch have different tags than 1/19 ? Please keep things
consistent ...

> ---
>  doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
> index 2fd8e7a..7abb746 100644
> --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
> +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
> @@ -7,6 +7,14 @@ Required properties:
>                 - The second index is for writing FPGA configuration data.
>  - resets     : Phandle and reset specifier for the device's reset.
>  - clocks     : Clocks used by the device.
> +- bitstream_periph : FPGA peripheral raw binary file which is used to
> +                     initialize FPGA IOs, PLL, IO48 and DDR.
> +- bitstream_core : FPGA core raw binary file contains FPGA design which is used
> +                   to program FPGA CRAM and ERAM.
> +- bitstream_devpart : Partition of flash device where bitstream files are
> +		       stored.
> +                      <dev[:part]> - dev is flash device number, part is flash
> +                                     device partition.
>  
>  Example:
>  
> @@ -16,4 +24,7 @@ Example:
>  		       0xffcfe400 0x20>;
>  		clocks = <&l4_mp_clk>;
>  		resets = <&rst FPGAMGR_RESET>;
> +		bitstream_periph = "ghrd_10as066n2.periph.rbf.mkimage";
> +		bitstream_core = "ghrd_10as066n2.core.rbf.mkimage";
> +		bitstream_devpart = "0:1";
>  	};
> 


-- 
Best regards,
Marek Vasut