[U-Boot] [PATCH v2 15/19] arm: socfpga: Add support to memory allocation in SPL

[Marek Vasut]

On 09/26/2017 07:06 AM, Chee, Tien Fong wrote:
> On Isn, 2017-09-25 at 11:21 +0200, Marek Vasut wrote:
>> On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
>>>
>>> From: Tien Fong Chee <tien.fong.chee at intel.com>
>>>
>>> Add support to memory allocation in SPL for preparation to enable
>>> FAT
>>> in SPL. Memory allocation is needed by FAT to work properly.
>>>
>>> Signed-off-by: Tien Fong Chee <tien.fong.chee at intel.com>
>> Gen 5 does have malloc support in SPL, so what's the deal here ?
>>
> For FAT to work properly in Arria 10 SPL, SPL malloc need to be
> enabled,

It is already enabled on Gen 5

> and the min of SPL malloc size is 0x2000.

Where did you find about this minimum ? That can be configured ...

> FAT needed in Arria
> 10 SPL, because u-boot.img is stored in FAT partition.

It can also be stored on ext partition (which is preferred, patent-wise)

>>>
>>> ---
>>>  include/configs/socfpga_common.h | 23 ++++++++++++++++++++++-
>>>  1 file changed, 22 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/include/configs/socfpga_common.h
>>> b/include/configs/socfpga_common.h
>>> index 7549ee8..9b6719e 100644
>>> --- a/include/configs/socfpga_common.h
>>> +++ b/include/configs/socfpga_common.h
>>> @@ -280,17 +280,34 @@ unsigned int
>>> cm_get_qspi_controller_clk_hz(void);
>>>  /*
>>>   * SPL
>>>   *
>>> - * SRAM Memory layout:
>>> + * SRAM Memory layout for gen 5:
>>>   *
>>>   * 0xFFFF_0000 ...... Start of SRAM
>>>   * 0xFFFF_xxxx ...... Top of stack (grows down)
>>>   * 0xFFFF_yyyy ...... Malloc area
>>>   * 0xFFFF_zzzz ...... Global Data
>>>   * 0xFFFF_FF00 ...... End of SRAM
>>> + *
>>> + * SRAM Memory layout for Arria 10:
>>> + * 0xFFE0_0000 ...... Start of SRAM (bottom)
>>> + * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
>>> + * 0xFFEy_yyyy ...... Malloc area (grows up to top)
>>> + * 0xFFEz_zzzz ...... Global Data
>>> + * 0xFFE3_FFFF ...... End of SRAM (top)
>>>   */
>>>  #define CONFIG_SPL_FRAMEWORK
>>>  #define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_AD
>>> DR
>>>  #define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_INIT_RAM_SIZ
>>> E
>>> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>>> +/* SPL memory allocation configuration, it is required by FAT
>>> feature */
>>> +#ifndef CONFIG_SYS_SPL_MALLOC_START
>>> +#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00002000
>>> +#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_INIT_RAM_SI
>>> ZE - \
>>> +					 GENERATED_GBL_DATA_SIZE -
>>> \
>>> +					 CONFIG_SYS_SPL_MALLOC_SIZ
>>> E + \
>>> +					 CONFIG_SYS_INIT_RAM_ADDR)
>>> +#endif
>>> +#endif
>>>  
>>>  /* SPL SDMMC boot support */
>>>  #ifdef CONFIG_SPL_MMC_SUPPORT
>>> @@ -320,7 +337,11 @@ unsigned int
>>> cm_get_qspi_controller_clk_hz(void);
>>>  /*
>>>   * Stack setup
>>>   */
>>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>>  #define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
>>> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>>> +#define CONFIG_SPL_STACK		(CONFIG_SYS_SPL_MALLOC_STA
>>> RT - 1)
>>> +#endif
>>>  
>>>  /* Extra Environment */
>>>  #ifndef CONFIG_SPL_BUILD
>>>


-- 
Best regards,
Marek Vasut