[U-Boot] [PATCH 003/080] mpc83xx: spd_sdram: Fix style violations

[Mario Six]

Fix style violations in the MPC83xx SPD-SDRAM code and make the code
more readable.

Signed-off-by: Mario Six <mario.six at gdsys.cc>
---
 arch/powerpc/cpu/mpc83xx/spd_sdram.c | 49 ++++++++++++++++--------------------
 1 file changed, 22 insertions(+), 27 deletions(-)

diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
index 48814a09f2..f9c41cbeb7 100644
--- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c
+++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
@@ -172,11 +172,10 @@ long int spd_sdram()
 	}
 
 	/* Check the number of physical bank */
-	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+	if (spd.mem_type == SPD_MEMTYPE_DDR)
 		n_ranks = spd.nrows;
-	} else {
+	else
 		n_ranks = (spd.nrows & 0x7) + 1;
-	}
 
 	if (n_ranks > 2) {
 		printf("DDR: The number of physical bank is %02X\n", n_ranks);
@@ -201,10 +200,9 @@ long int spd_sdram()
 	/*
 	 * Adjust DDR II IO voltage biasing.  It just makes it work.
 	 */
-	if(spd.mem_type == SPD_MEMTYPE_DDR2) {
+	if (spd.mem_type == SPD_MEMTYPE_DDR2)
 		immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
-	}
-	udelay(50000);
+	mdelay(50);
 #endif
 
 	/*
@@ -212,14 +210,13 @@ long int spd_sdram()
 	 */
 	odt_rd_cfg = 0;			/* Never assert ODT */
 	odt_wr_cfg = 0;			/* Never assert ODT */
-	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+	if (spd.mem_type == SPD_MEMTYPE_DDR2)
 		odt_wr_cfg = 1;		/* Assert ODT on writes to CSn */
-	}
 
 	/* Setup DDR chip select register */
 #ifdef CONFIG_SYS_83XX_DDR_USES_CS0
 	ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
-	ddr->cs_config[0] = ( 1 << 31
+	ddr->cs_config[0] = (BIT(31)
 			    | (odt_rd_cfg << 20)
 			    | (odt_wr_cfg << 16)
 			    | ((spd.nbanks == 8 ? 1 : 0) << 14)
@@ -230,9 +227,9 @@ long int spd_sdram()
 	debug("cs0_config = 0x%08x\n", ddr->cs_config[0]);
 
 	if (n_ranks == 2) {
-		ddr->cs_config[1] = ( 1<<31
 		ddr->csbnds[1].csbnds = ((banksize(spd.row_dens) >> 8)
 				  | ((banksize(spd.row_dens) >> 23) - 1));
+		ddr->cs_config[1] = (BIT(31)
 				    | (odt_rd_cfg << 20)
 				    | (odt_wr_cfg << 16)
 				    | ((spd.nbanks == 8 ? 1 : 0) << 14)
@@ -244,7 +241,7 @@ long int spd_sdram()
 
 #else
 	ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
-	ddr->cs_config[2] = ( 1 << 31
+	ddr->cs_config[2] = (BIT(31)
 			    | (odt_rd_cfg << 20)
 			    | (odt_wr_cfg << 16)
 			    | ((spd.nbanks == 8 ? 1 : 0) << 14)
@@ -255,9 +252,9 @@ long int spd_sdram()
 	debug("cs2_config = 0x%08x\n", ddr->cs_config[2]);
 
 	if (n_ranks == 2) {
-		ddr->cs_config[3] = ( 1<<31
 		ddr->csbnds[3].csbnds = ((banksize(spd.row_dens) >> 8)
 				  | ((banksize(spd.row_dens) >> 23) - 1));
+		ddr->cs_config[3] = (BIT(31)
 				    | (odt_rd_cfg << 20)
 				    | (odt_wr_cfg << 16)
 				    | ((spd.nbanks == 8 ? 1 : 0) << 14)
@@ -445,11 +442,10 @@ long int spd_sdram()
 	 * Convert caslat clocks to DDR controller value.
 	 * Force caslat_ctrl to be DDR Controller field-sized.
 	 */
-	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+	if (spd.mem_type == SPD_MEMTYPE_DDR)
 		caslat_ctrl = (caslat + 1) & 0x07;
-	} else {
+	else
 		caslat_ctrl =  (2 * caslat - 1) & 0x0f;
-	}
 
 	debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
 	debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
@@ -547,13 +543,12 @@ long int spd_sdram()
 	 *	add_lat + caslat must be >= 4
 	 */
 	add_lat = 0;
-	if (spd.mem_type == SPD_MEMTYPE_DDR2
-	    && (odt_wr_cfg || odt_rd_cfg)
-	    && (caslat < 4)) {
+	if (spd.mem_type == SPD_MEMTYPE_DDR2 &&
+	    (odt_wr_cfg || odt_rd_cfg) &&
+	    caslat < 4) {
 		add_lat = 4 - caslat;
-		if ((add_lat + caslat) < 4) {
+		if ((add_lat + caslat) < 4)
 			add_lat = 0;
-		}
 	}
 
 	/*
@@ -652,7 +647,7 @@ long int spd_sdram()
 		debug(" without ECC\n");
 
 	/* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
-	   Burst type is sequential
+	 * Burst type is sequential
 	 */
 	if (spd.mem_type == SPD_MEMTYPE_DDR) {
 		switch (caslat) {
@@ -685,9 +680,9 @@ long int spd_sdram()
 
 		ddr->sdram_mode =
 			(0
-			 | (1 << (16 + 10))             /* DQS Differential disable */
+			 | BIT(16 + 10)                 /* DQS Differential disable */
 #ifdef CONFIG_SYS_DDR_MODE_WEAK
-			 | (1 << (16 + 1))		/* weak driver (~60%) */
+			 | BIT(16 + 1)		        /* weak driver (~60%) */
 #endif
 			 | (add_lat << (16 + 3))        /* Additive Latency in EMRS1 */
 			 | (mode_odt_enable << 16)      /* ODT Enable in EMRS1 */
@@ -746,9 +741,8 @@ long int spd_sdram()
 	 */
 	odt_cfg = 0;
 #ifndef CONFIG_NEVER_ASSERT_ODT_TO_CPU
-	if (odt_rd_cfg | odt_wr_cfg) {
+	if (odt_rd_cfg | odt_wr_cfg)
 		odt_cfg = 0x2;		/* ODT to IOs during reads */
-	}
 #endif
 	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
 		ddr->sdram_cfg2 = (0
@@ -816,7 +810,8 @@ long int spd_sdram()
 		/* disable error detection */
 		ddr->err_disable = ~ECC_ERROR_ENABLE;
 		/* set single bit error threshold to maximum value,
-		 * reset counter to zero */
+		 * reset counter to zero
+		 */
 		ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
 				(0 << ECC_ERROR_MAN_SBEC_SHIFT);
 	}
@@ -847,7 +842,7 @@ long int spd_sdram()
  * Use timebase counter, get_timer() is not available
  * at this point of initialization yet.
  */
-static __inline__ unsigned long get_tbms (void)
+static inline unsigned long get_tbms (void)
 {
 	unsigned long tbl;
 	unsigned long tbu1, tbu2;
-- 
2.11.0