[U-Boot] [U-Boot, 10/36] rockchip: rk322x: prepare to use common board file
Philipp Tomsich
philipp.tomsich at theobroma-systems.com
Sun Apr 1 21:06:07 UTC 2018
On Tue, 27 Mar 2018, Kever Yang wrote:
> Move soc spec setting into rk322x.c and remove rk322x-board/board-spl.c
A clear description of what the patch is attempting to achieve.
>
> Signed-off-by: Kever Yang <kever.yang at rock-chips.com>
See below for requested changes.
> ---
>
> arch/arm/mach-rockchip/rk322x-board.c | 155 ---------------------
> arch/arm/mach-rockchip/rk322x/Makefile | 2 +-
> .../{rk322x-board-spl.c => rk322x/rk322x.c} | 86 ++++--------
> 3 files changed, 29 insertions(+), 214 deletions(-)
> delete mode 100644 arch/arm/mach-rockchip/rk322x-board.c
> rename arch/arm/mach-rockchip/{rk322x-board-spl.c => rk322x/rk322x.c} (51%)
>
> diff --git a/arch/arm/mach-rockchip/rk322x-board.c b/arch/arm/mach-rockchip/rk322x-board.c
> deleted file mode 100644
> index 8642a90..0000000
> --- a/arch/arm/mach-rockchip/rk322x-board.c
> +++ /dev/null
> @@ -1,155 +0,0 @@
> -/*
> - * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -#include <common.h>
> -#include <clk.h>
> -#include <dm.h>
> -#include <ram.h>
> -#include <syscon.h>
> -#include <asm/io.h>
> -#include <asm/arch/clock.h>
> -#include <asm/arch/periph.h>
> -#include <asm/arch/grf_rk322x.h>
> -#include <asm/arch/boot_mode.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -__weak int rk_board_late_init(void)
> -{
> - return 0;
> -}
> -
> -int board_late_init(void)
> -{
> - setup_boot_mode();
> -
> - return rk_board_late_init();
> -}
> -
> -int board_init(void)
> -{
> -#include <asm/arch/grf_rk322x.h>
> - /* Enable early UART2 channel 1 on the RK322x */
> -#define GRF_BASE 0x11000000
> - struct rk322x_grf * const grf = (void *)GRF_BASE;
> - enum {
> - GPIO1B2_SHIFT = 4,
> - GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
> - GPIO1B2_GPIO = 0,
> - GPIO1B2_UART21_SIN,
> -
> - GPIO1B1_SHIFT = 2,
> - GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
> - GPIO1B1_GPIO = 0,
> - GPIO1B1_UART1_SOUT,
> - GPIO1B1_UART21_SOUT,
> - };
> - enum {
> - CON_IOMUX_UART2SEL_SHIFT= 8,
> - CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
> - CON_IOMUX_UART2SEL_2 = 0,
> - CON_IOMUX_UART2SEL_21,
> - };
> -
> - rk_clrsetreg(&grf->gpio1b_iomux,
> - GPIO1B1_MASK | GPIO1B2_MASK,
> - GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
> - GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
> - /* Set channel C as UART2 input */
> - rk_clrsetreg(&grf->con_iomux,
> - CON_IOMUX_UART2SEL_MASK,
> - CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
> -
> - /*
> - * The integrated macphy is enabled by default, disable it
> - * for saving power consuming.
> - */
> - rk_clrsetreg(&grf->macphy_con[0],
> - MACPHY_CFG_ENABLE_MASK,
> - 0 << MACPHY_CFG_ENABLE_SHIFT);
> -
> - return 0;
> -}
> -
> -int dram_init_banksize(void)
> -{
> - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
> - gd->bd->bi_dram[0].size = 0x8400000;
> - /* Reserve 0x200000 for OPTEE */
> - gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
> - + gd->bd->bi_dram[0].size + 0x200000;
> - gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
> - + gd->ram_size - gd->bd->bi_dram[1].start;
> -
> - return 0;
> -}
> -
> -#ifndef CONFIG_SYS_DCACHE_OFF
> -void enable_caches(void)
> -{
> - /* Enable D-cache. I-cache is already enabled in start.S */
> - dcache_enable();
> -}
> -#endif
> -
> -#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
> -#include <usb.h>
> -#include <usb/dwc2_udc.h>
> -
> -static struct dwc2_plat_otg_data rk322x_otg_data = {
> - .rx_fifo_sz = 512,
> - .np_tx_fifo_sz = 16,
> - .tx_fifo_sz = 128,
> -};
> -
> -int board_usb_init(int index, enum usb_init_type init)
> -{
> - int node;
> - const char *mode;
> - bool matched = false;
> - const void *blob = gd->fdt_blob;
> -
> - /* find the usb_otg node */
> - node = fdt_node_offset_by_compatible(blob, -1,
> - "rockchip,rk3288-usb");
> -
> - while (node > 0) {
> - mode = fdt_getprop(blob, node, "dr_mode", NULL);
> - if (mode && strcmp(mode, "otg") == 0) {
> - matched = true;
> - break;
> - }
> -
> - node = fdt_node_offset_by_compatible(blob, node,
> - "rockchip,rk3288-usb");
> - }
> - if (!matched) {
> - debug("Not found usb_otg device\n");
> - return -ENODEV;
> - }
> - rk322x_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
> -
> - return dwc2_udc_probe(&rk322x_otg_data);
> -}
> -
> -int board_usb_cleanup(int index, enum usb_init_type init)
> -{
> - return 0;
> -}
> -#endif
> -
> -#if defined(CONFIG_USB_FUNCTION_FASTBOOT)
> -int fb_set_reboot_flag(void)
> -{
> - struct rk322x_grf *grf;
> -
> - printf("Setting reboot to fastboot flag ...\n");
> - grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> - /* Set boot mode to fastboot */
> - writel(BOOT_FASTBOOT, &grf->os_reg[0]);
> -
> - return 0;
> -}
> -#endif
> diff --git a/arch/arm/mach-rockchip/rk322x/Makefile b/arch/arm/mach-rockchip/rk322x/Makefile
> index ecb3e8d..89b0fed 100644
> --- a/arch/arm/mach-rockchip/rk322x/Makefile
> +++ b/arch/arm/mach-rockchip/rk322x/Makefile
> @@ -4,6 +4,6 @@
> # SPDX-License-Identifier: GPL-2.0+
> #
>
> -
> obj-y += clk_rk322x.o
> +obj-y += rk322x.o
> obj-y += syscon_rk322x.o
> diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x/rk322x.c
> similarity index 51%
> rename from arch/arm/mach-rockchip/rk322x-board-spl.c
> rename to arch/arm/mach-rockchip/rk322x/rk322x.c
> index 206abfa..98b6ec3 100644
> --- a/arch/arm/mach-rockchip/rk322x-board-spl.c
> +++ b/arch/arm/mach-rockchip/rk322x/rk322x.c
> @@ -1,32 +1,41 @@
> /*
> - * (C) Copyright 2017 Rockchip Electronics Co., Ltd
> + * Copyright (c) 2017 Rockchip Electronics Co., Ltd
> *
> * SPDX-License-Identifier: GPL-2.0+
> */
> -
> -#include <common.h>
> -#include <debug_uart.h>
> -#include <dm.h>
> -#include <ram.h>
> -#include <spl.h>
> #include <asm/io.h>
> #include <asm/arch/bootrom.h>
> -#include <asm/arch/cru_rk322x.h>
> -#include <asm/arch/grf_rk322x.h>
> #include <asm/arch/hardware.h>
> -#include <asm/arch/timer.h>
> -#include <asm/arch/uart.h>
> +#include <asm/arch/grf_rk322x.h>
>
> -u32 spl_boot_device(void)
> +#define GRF_BASE 0x11000000
> +#define CRU_MISC_CON 0x110e0134
> +#define SGRF_DDR_CON0 0x10150000
Please use 'const' and declare within functions, if used only by a single
function.
> +
> +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
> + [BROM_BOOTSOURCE_EMMC] = "/sdhci at fe330000",
> + [BROM_BOOTSOURCE_SD] = "/dwmmc at fe320000",
> +};
> +
> +#ifdef CONFIG_SPL_BUILD
> +int arch_cpu_init(void)
> {
> - return BOOT_DEVICE_MMC1;
> -}
> -DECLARE_GLOBAL_DATA_PTR;
> + static struct rk322x_grf * const grf = (void *)GRF_BASE;
> + /* We do some SoC one time setting here. */
>
> -#define GRF_BASE 0x11000000
> -#define SGRF_BASE 0x10140000
> + /* Disable the ddr secure region setting to make it non-secure */
> + rk_clrreg(SGRF_DDR_CON0, 0x4000);
> +
> + /*
> + * The integrated macphy is enabled by default, disable it
> + * for saving power consuming.
> + */
> + rk_clrsetreg(&grf->macphy_con[0], MACPHY_CFG_ENABLE_MASK,
> + 0 << MACPHY_CFG_ENABLE_SHIFT);
>
> -#define DEBUG_UART_BASE 0x11030000
> + return 0;
> +}
> +#endif
>
> void board_debug_uart_init(void)
> {
> @@ -34,8 +43,7 @@ void board_debug_uart_init(void)
> enum {
> GPIO1B2_SHIFT = 4,
> GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
> - GPIO1B2_GPIO = 0,
> - GPIO1B2_UART1_SIN,
> + GPIO1B2_GPIO = 0,
> GPIO1B2_UART21_SIN,
This looks odd: are you shure this is 'GPIO1B2_UART21_SIN'?
>
> GPIO1B1_SHIFT = 2,
> @@ -61,41 +69,3 @@ void board_debug_uart_init(void)
> CON_IOMUX_UART2SEL_MASK,
> CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
> }
> -
> -#define SGRF_DDR_CON0 0x10150000
> -void board_init_f(ulong dummy)
> -{
> - struct udevice *dev;
> - int ret;
> -
> - /*
> - * Debug UART can be used from here if required:
> - *
> - * debug_uart_init();
> - * printch('a');
> - * printhex8(0x1234);
> - * printascii("string");
> - */
> - debug_uart_init();
> - printascii("SPL Init");
> -
> - ret = spl_early_init();
> - if (ret) {
> - debug("spl_early_init() failed: %d\n", ret);
> - hang();
> - }
> -
> - rockchip_timer_init();
> - printf("timer init done\n");
> - ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> - if (ret) {
> - printf("DRAM init failed: %d\n", ret);
> - return;
> - }
> -
> - /* Disable the ddr secure region setting to make it non-secure */
> - rk_clrreg(SGRF_DDR_CON0, 0x4000);
> -#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
> - back_to_bootrom(BROM_BOOT_NEXTSTAGE);
> -#endif
> -}
>
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