[U-Boot] [PATCH v4 1/2] SPI Flash: add support of sst26wf* flash ICs protection ops
Jagan Teki
jagannadh.teki at gmail.com
Mon Apr 9 11:22:41 UTC 2018
On Mon, Apr 9, 2018 at 4:27 PM, Eugeniy Paltsev
<Eugeniy.Paltsev at synopsys.com> wrote:
> sst26wf flash series block protection implementation differs
> from other SST series, so add specific implementation
> flash_lock/flash_unlock/flash_is_locked functions for sst26wf
> flash ICs.
>
> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com>
> ---
> Changes v3->v4:
> * Make sst26_process_bpr() and sst26_lock_ctl() functions static.
>
> Changes v2->v3:
> * Move SST26 command defenition to sf_internal.h
> * Merge sst26_set_bpr, sst26_clear_bpr and sst26_check_bpr functions
> into single sst26_process_bpr function.
> * Use SF_UNLOCKED/SF_LOCKED instead of magic numbers in
> sst26_lock_ctl()
>
> Changes v1->v2:
> * Use generic defines from linux/sizes.h instead of custom ones.
>
> drivers/mtd/spi/sf_internal.h | 18 +++++
> drivers/mtd/spi/spi_flash.c | 165 ++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 183 insertions(+)
>
> diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
> index 839cdbe1b0..a17dcc4de1 100644
> --- a/drivers/mtd/spi/sf_internal.h
> +++ b/drivers/mtd/spi/sf_internal.h
> @@ -26,6 +26,11 @@ enum spi_nor_option_flags {
> SNOR_F_USE_UPAGE = BIT(3),
> };
>
> +enum flash_lock_status {
> + SF_UNLOCKED = 0,
> + SF_LOCKED = 1,
> +};
Try to use existing relevant error codes.
> +
> #define SPI_FLASH_3B_ADDR_LEN 3
> #define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
> #define SPI_FLASH_16MB_BOUN 0x1000000
> @@ -87,6 +92,19 @@ enum spi_nor_option_flags {
>
> /* SST specific */
> #ifdef CONFIG_SPI_FLASH_SST
> +#define SST26_CMD_READ_BPR 0x72
> +#define SST26_CMD_WRITE_BPR 0x42
> +
> +#define SST26_BPR_8K_NUM 4
> +#define SST26_MAX_BPR_REG_LEN (18 + 1)
> +#define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K)
> +
> +enum lock_ctl {
> + CTL_LOCK,
> + CTL_UNLOCK,
> + CTL_CHECK
> +};
SST26_CTL_* ?
> +
> # define CMD_SST_BP 0x02 /* Byte Program */
> # define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */
>
> diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
> index 2e61685d3e..0f4e7fd5d4 100644
> --- a/drivers/mtd/spi/spi_flash.c
> +++ b/drivers/mtd/spi/spi_flash.c
> @@ -16,6 +16,7 @@
> #include <spi.h>
> #include <spi_flash.h>
> #include <linux/log2.h>
> +#include <linux/sizes.h>
> #include <dma.h>
>
> #include "sf_internal.h"
> @@ -842,6 +843,161 @@ int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len)
> }
> #endif
>
> +#if defined(CONFIG_SPI_FLASH_SST)
Please move this code inside of existing #ifdef of SST (commented same
in previous version)
> +static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl)
> +{
> + switch (ctl) {
> + case CTL_LOCK:
> + cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8);
> + break;
> + case CTL_UNLOCK:
> + cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8);
> + break;
> + case CTL_CHECK:
> + return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8));
> + }
> +
> + return false;
> +}
> +
> +/*
> + * sst26wf016/sst26wf032/sst26wf064 have next block protection:
> + * 4x - 8 KByte blocks - read & write protection bits - upper addresses
> + * 1x - 32 KByte blocks - write protection bits
> + * rest - 64 KByte blocks - write protection bits
> + * 1x - 32 KByte blocks - write protection bits
> + * 4x - 8 KByte blocks - read & write protection bits - lower addresses
> + *
> + * We'll support only per 64k lock/unlock so lower and upper 64 KByte region
> + * will be treated as single block.
> + */
> +
> +/*
> + * Lock, unlock or check lock status of the flash region of the flash (depending
> + * on the lock_ctl value)
> + */
> +static int sst26_lock_ctl(struct spi_flash *flash, u32 ofs, size_t len, enum lock_ctl ctl)
> +{
> + u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size;
> + bool lower_64k = false, upper_64k = false;
> + u8 cmd, bpr_buff[SST26_MAX_BPR_REG_LEN] = {};
> + int ret;
> +
> + /* Check length and offset for 64k alignment */
> + if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1)))
> + return -EINVAL;
> +
> + if (ofs + len > flash->size)
> + return -EINVAL;
> +
> + /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */
> + if (flash->size != SZ_2M &&
> + flash->size != SZ_4M &&
> + flash->size != SZ_8M)
> + return -EINVAL;
> +
> + bpr_size = 2 + (flash->size / SZ_64K / 8);
> +
> + cmd = SST26_CMD_READ_BPR;
> + ret = spi_flash_read_common(flash, &cmd, 1, bpr_buff, bpr_size);
> + if (ret < 0) {
> + printf("SF: fail to read block-protection register\n");
> + return ret;
> + }
> +
> + rptr_64k = min_t(u32, ofs + len , flash->size - SST26_BOUND_REG_SIZE);
> + lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE);
> +
> + upper_64k = ((ofs + len) > (flash->size - SST26_BOUND_REG_SIZE));
> + lower_64k = (ofs < SST26_BOUND_REG_SIZE);
> +
> + /* Lower bits in block-protection register are about 64k region */
> + bpr_ptr = lptr_64k / SZ_64K - 1;
> +
> + /* Process 64K blocks region */
> + while (lptr_64k < rptr_64k) {
> + if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
> + return SF_LOCKED;
> +
> + bpr_ptr++;
> + lptr_64k += SZ_64K;
> + }
> +
> + /* 32K and 8K region bits in BPR are after 64k region bits */
> + bpr_ptr = (flash->size - 2 * SST26_BOUND_REG_SIZE) / SZ_64K;
> +
> + /* Process lower 32K block region */
> + if (lower_64k)
> + if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
> + return SF_LOCKED;
> +
> + bpr_ptr++;
> +
> + /* Process upper 32K block region */
> + if (upper_64k)
> + if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
> + return SF_LOCKED;
> +
> + bpr_ptr++;
> +
> + /* Process lower 8K block regions */
> + for (i = 0; i < SST26_BPR_8K_NUM; i++) {
> + if (lower_64k)
> + if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
> + return SF_LOCKED;
> +
> + /* In 8K area BPR has both read and write protection bits */
> + bpr_ptr += 2;
> + }
> +
> + /* Process upper 8K block regions */
> + for (i = 0; i < SST26_BPR_8K_NUM; i++) {
> + if (upper_64k)
> + if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
> + return SF_LOCKED;
> +
> + /* In 8K area BPR has both read and write protection bits */
> + bpr_ptr += 2;
> + }
> +
> + /* If we check region status we don't need to write BPR back */
> + if (ctl == CTL_CHECK)
> + return SF_UNLOCKED;
> +
> + cmd = SST26_CMD_WRITE_BPR;
> + ret = spi_flash_write_common(flash, &cmd, 1, bpr_buff, bpr_size);
> + if (ret < 0) {
> + printf("SF: fail to write block-protection register\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int sst26_unlock(struct spi_flash *flash, u32 ofs, size_t len)
> +{
> + return sst26_lock_ctl(flash, ofs, len, CTL_UNLOCK);
> +}
> +
> +static int sst26_lock(struct spi_flash *flash, u32 ofs, size_t len)
> +{
> + return sst26_lock_ctl(flash, ofs, len, CTL_LOCK);
> +}
> +
> +static int sst26_is_locked(struct spi_flash *flash, u32 ofs, size_t len)
> +{
> + /*
> + * is_locked function is used for check before reading or erasing flash
> + * region, so offset and length might be not 64k allighned, so adjust
> + * them to be 64k allighned as sst26_lock_ctl works only with 64k
> + * allighned regions.
> + */
> + ofs -= ofs & (SZ_64K - 1);
> + len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len;
> +
> + return sst26_lock_ctl(flash, ofs, len, CTL_CHECK);
> +}
> +#endif
>
> #ifdef CONFIG_SPI_FLASH_MACRONIX
> static int macronix_quad_enable(struct spi_flash *flash)
> @@ -1033,6 +1189,15 @@ int spi_flash_scan(struct spi_flash *flash)
> }
> #endif
>
> +/* sst26wf series block protection implementation differs from other series */
> +#if defined(CONFIG_SPI_FLASH_SST)
> + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST && info->id[1] == 0x26) {
> + flash->flash_lock = sst26_lock;
> + flash->flash_unlock = sst26_unlock;
> + flash->flash_is_locked = sst26_is_locked;
> + }
> +#endif
Previous version comment need to fix here? (about switch case with
existing lock ops)?
Jagan.
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