[U-Boot] [PATCH 19/19] spi: mpc8xxx: Add DM support

[Mario Six]

Support DM for the MPC8XXX SPI driver.

Signed-off-by: Mario Six <mario.six at gdsys.cc>
---
 drivers/spi/mpc8xxx_spi.c | 135 +++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 133 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c
index 5724a00585..6e51826665 100644
--- a/drivers/spi/mpc8xxx_spi.c
+++ b/drivers/spi/mpc8xxx_spi.c
@@ -10,6 +10,11 @@
 #include <malloc.h>
 #include <spi.h>
 #include <asm/mpc8xxx_spi.h>
+#ifdef CONFIG_DM_SPI
+#include <errno.h>
+#include <dm.h>
+#include <asm-generic/gpio.h>
+#endif
 
 enum {
 	SPI_EV_NE = BIT(31 - 22),	/* Receiver Not Empty */
@@ -31,6 +36,14 @@ enum {
 	SPI_COM_LST = BIT(31 - 9),
 };
 
+#ifdef CONFIG_DM_SPI
+struct mpc8xxx_priv {
+	spi8xxx_t *spi;
+	struct gpio_desc gpios[16];
+	int max_cs;
+};
+#endif
+
 static inline u32 to_prescale_mod(u32 val)
 {
 	return (min(val, (u32)15) << 16);
@@ -54,7 +67,7 @@ static void __spi_init_head(spi8xxx_t *spi)
 
 static int __spi_set_speed(spi8xxx_t *spi, uint speed)
 {
-	/* TODO: This only ever sets one fixed speed */
+	/* TODO(mario.six at gdsys.cc): This only ever sets one fixed speed */
 
 	/* Use SYSCLK / 8 (16.67MHz typ.) */
 	clrsetbits_be32(&spi->mode, SPI_MODE_PM_MASK, to_prescale_mod(1));
@@ -75,7 +88,7 @@ static void __spi_init_tail(spi8xxx_t *spi)
 static int __spi_xfer(spi8xxx_t *spi, uint bitlen, const u8 *dout, u8 *din,
 		      ulong flags)
 {
-	u32 tmpdin;
+	u32 tmpdin = 0;
 	int num_blks = DIV_ROUND_UP(bitlen, 32);
 
 	/* Clear all SPI events */
@@ -159,6 +172,110 @@ static int __spi_xfer(spi8xxx_t *spi, uint bitlen, const u8 *dout, u8 *din,
 	return 0;
 }
 
+#ifdef CONFIG_DM_SPI
+
+static int mpc8xxx_spi_ofdata_to_platdata(struct udevice *dev)
+{
+	struct mpc8xxx_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	priv->spi = (spi8xxx_t *)dev_read_addr(dev);
+
+	/* TODO(mario.six at gdsys.cc): Read clock and save the value */
+
+	ret = gpio_request_list_by_name(dev, "gpios", priv->gpios,
+					ARRAY_SIZE(priv->gpios), GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
+	if (ret < 0)
+		return -EINVAL;
+
+	priv->max_cs = ret;
+
+	return 0;
+}
+
+static int mpc8xxx_spi_probe(struct udevice *dev)
+{
+	struct mpc8xxx_priv *priv = dev_get_priv(dev);
+
+	__spi_init_head(priv->spi);
+	__spi_set_speed(priv->spi, 16666667);
+	__spi_init_tail(priv->spi);
+
+	return 0;
+}
+
+static void mpc8xxx_spi_cs_activate(struct udevice *dev)
+{
+	struct mpc8xxx_priv *priv = dev_get_priv(dev->parent);
+	struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
+
+	dm_gpio_set_dir_flags(&priv->gpios[platdata->cs], GPIOD_IS_OUT);
+	dm_gpio_set_value(&priv->gpios[platdata->cs], 0);
+}
+
+static void mpc8xxx_spi_cs_deactivate(struct udevice *dev)
+{
+	struct mpc8xxx_priv *priv = dev_get_priv(dev->parent);
+	struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
+
+	dm_gpio_set_dir_flags(&priv->gpios[platdata->cs], GPIOD_IS_OUT);
+	dm_gpio_set_value(&priv->gpios[platdata->cs], 1);
+}
+
+static int mpc8xxx_spi_xfer(struct udevice *dev, uint bitlen,
+			    const void *dout, void *din, ulong flags)
+{
+	int ret;
+	struct udevice *bus = dev->parent;
+	struct mpc8xxx_priv *priv = dev_get_priv(bus);
+	struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
+
+	debug("%s: slave %s:%u dout %08X din %08X bitlen %u\n", __func__,
+	      bus->name, platdata->cs, *(uint *)dout, *(uint *)din, bitlen);
+
+	if (flags & SPI_XFER_BEGIN)
+		mpc8xxx_spi_cs_activate(dev);
+
+	ret = __spi_xfer(priv->spi, bitlen, dout, din, flags);
+
+	if (flags & SPI_XFER_END)
+		mpc8xxx_spi_cs_deactivate(dev);
+
+	return ret;
+}
+
+static int mpc8xxx_spi_set_speed(struct udevice *dev, uint speed)
+{
+	struct mpc8xxx_priv *priv = dev_get_priv(dev);
+
+	return __spi_set_speed(priv->spi, speed);
+}
+
+static int mpc8xxx_spi_set_mode(struct udevice *dev, uint mode)
+{
+	/* TODO(mario.six at gdsys.cc): Using SPI_CPHA (for clock phase) and
+	 * SPI_CPOL (for clock polarity) should work
+	 */
+	return 0;
+}
+
+static const struct dm_spi_ops mpc8xxx_spi_ops = {
+	.xfer		= mpc8xxx_spi_xfer,
+	.set_speed	= mpc8xxx_spi_set_speed,
+	.set_mode	= mpc8xxx_spi_set_mode,
+	/*
+	 * cs_info is not needed, since we require all chip selects to be
+	 * in the device tree explicitly
+	 */
+};
+
+static const struct udevice_id mpc8xxx_spi_ids[] = {
+	{ .compatible = "fsl,spi" },
+	{ }
+};
+
+#else
+
 struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode)
 {
 	struct spi_slave *slave;
@@ -221,3 +338,17 @@ int spi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, void *din,
 
 	return ret;
 }
+
+#endif
+
+#ifdef CONFIG_DM_SPI
+U_BOOT_DRIVER(mpc8xxx_spi) = {
+	.name	= "mpc8xxx_spi",
+	.id	= UCLASS_SPI,
+	.of_match = mpc8xxx_spi_ids,
+	.ops	= &mpc8xxx_spi_ops,
+	.ofdata_to_platdata = mpc8xxx_spi_ofdata_to_platdata,
+	.probe	= mpc8xxx_spi_probe,
+	.priv_auto_alloc_size = sizeof(struct mpc8xxx_priv),
+};
+#endif
-- 
2.11.0