[U-Boot] [PATCH 1/8] rockchip: add STIMER_BASE for Rockchip SoCs

[Kever Yang]

Most of Rockchip SoCs have ARM arch/generic timer whose clock source
is from one of secure timer(if the soc supports Trust environment).

STIMER can only access in secure mode, so it should be init before
the proper U-Boot(usually in non-secure mode).
Add a MACRO for timer base addr so that we can init with a common
function in SPL/TPL.

Signed-off-by: Kever Yang <kever.yang at rock-chips.com>
---

 arch/arm/mach-rockchip/Kconfig | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 0adaed4..55d3d5c 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -191,6 +191,22 @@ config ROCKCHIP_BOOT_MODE_REG
 	  The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h)
 	  according to the value from this register.
 
+config ROCKCHIP_STIMER_BASE
+	hex "Rockchip Secure timer base address"
+	default 0x200440a0 if ROCKCHIP_RK3036
+	default 0x20018020 if ROCKCHIP_RK3126
+	default 0x200440a0 if ROCKCHIP_RK3128
+	default 0x110d0020 if ROCKCHIP_RK322X
+	default 0xff810020 if ROCKCHIP_RK3288
+	default 0xff1d0020 if ROCKCHIP_RK3328
+	default 0xff830020 if ROCKCHIP_RK3368
+	default 0xff8680a0 if ROCKCHIP_RK3399
+	default 0x10350020 if ROCKCHIP_RV1108
+	default 0
+	help
+	  The secure timer inited in SPL/TPL in secure word, ARM generic timer
+	  works after this timer work.
+
 config ROCKCHIP_SPL_RESERVE_IRAM
 	hex "Size of IRAM reserved in SPL"
 	default 0
-- 
1.9.1