[U-Boot] [PATCH v1 07/16] arm: socfpga: stratix10: Add misc support for Stratix10 SoC

[Marek Vasut]

On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
> Add misc support such as EMAC and cpu info printout for Stratix SoC
> 
> Signed-off-by: Chin Liang See <chin.liang.see at intel.com>
> Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>
> ---
>  arch/arm/mach-socfpga/Makefile   |    1 +
>  arch/arm/mach-socfpga/misc_s10.c |  103 ++++++++++++++++++++++++++++++++++++++
>  2 files changed, 104 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/mach-socfpga/misc_s10.c
> 
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index 910eb6f..b253914 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -32,6 +32,7 @@ endif
>  
>  ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
>  obj-y	+= clock_manager_s10.o
> +obj-y	+= misc_s10.o
>  obj-y	+= reset_manager_s10.o
>  obj-y	+= system_manager_s10.o
>  obj-y	+= wrap_pinmux_config_s10.o
> diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
> new file mode 100644
> index 0000000..b1cc6ca
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/misc_s10.c
> @@ -0,0 +1,103 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
> + *
> + */
> +
> +#include <altera.h>
> +#include <common.h>
> +#include <errno.h>
> +#include <fdtdec.h>
> +#include <miiphy.h>
> +#include <netdev.h>
> +#include <watchdog.h>
> +#include <asm/io.h>
> +#include <asm/arch/reset_manager.h>
> +#include <asm/arch/system_manager.h>
> +#include <asm/arch/misc.h>
> +#include <asm/pl310.h>
> +#include <linux/libfdt.h>
> +
> +#include <dt-bindings/reset/altr,rst-mgr-s10.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static struct socfpga_system_manager *sysmgr_regs =
> +	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> +
> +/*
> + * DesignWare Ethernet initialization
> + */
> +#ifdef CONFIG_ETH_DESIGNWARE

Use the reset framework ? Talk to Dinh if in doubt

> +void dwmac_deassert_reset(const unsigned int of_reset_id,
> +			  const u32 phymode)
> +{
> +	/* Put the emac we're using into reset.
> +	 * This is required before configuring the PHY interface
> +	 */
> +	socfpga_emac_manage_reset(of_reset_id, 1);
> +
> +	clrsetbits_le32(&sysmgr_regs->emac0 + (of_reset_id - EMAC0_RESET),
> +			SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
> +			phymode);
> +
> +	socfpga_emac_manage_reset(of_reset_id, 0);
> +}
> +#endif
> +
> +/*
> + * Print CPU information
> + */
> +#if defined(CONFIG_DISPLAY_CPUINFO)
> +int print_cpuinfo(void)
> +{
> +	puts("CPU:   Intel FPGA SoCFPGA Platform\n");
> +	puts("FPGA:  Intel FPGA Stratix 10\n");

This can well come from DT.

> +	return 0;
> +}
> +#endif
> +
> +#ifdef CONFIG_ARCH_MISC_INIT
> +int arch_misc_init(void)
> +{
> +	char qspi_string[13];
> +
> +	sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
> +	env_set("qspi_clock", qspi_string);
> +
> +	return socfpga_eth_reset();
> +}
> +#endif
> +
> +int arch_early_init_r(void)
> +{
> +	return 0;

Needed ?

> +}
> +
> +int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> +{
> +	if (argc != 2)
> +		return CMD_RET_USAGE;
> +
> +	argv++;
> +
> +	switch (*argv[0]) {
> +	case 'e':	/* Enable */
> +		socfpga_bridges_reset(1);
> +		break;
> +	case 'd':	/* Disable */
> +		socfpga_bridges_reset(0);
> +		break;

Do you really need to duplicate this command ?

> +	default:
> +		return CMD_RET_USAGE;
> +	}
> +
> +	return 0;
> +}
> +
> +U_BOOT_CMD(bridge, 2, 1, do_bridge,
> +	   "SoCFPGA HPS FPGA bridge control",
> +	   "enable  - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
> +	   "bridge disable - Disable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
> +	   ""
> +);
> 


-- 
Best regards,
Marek Vasut