[U-Boot] [RFC PATCH] arm: zynqmp: Add ZynqMP minimal R5 support
Michal Simek
michal.simek at xilinx.com
Fri Apr 20 07:09:45 UTC 2018
Hi Alex,
On 19.4.2018 18:48, Alexander Graf wrote:
> On 04/18/2018 03:11 PM, Michal Simek wrote:
>> Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot.
>> This patch is adding minimal support to get U-Boot boot.
>> DDR needs to be partitioned. Console is done via Cadence uart driver and
>> the first Cadence Triple Timer Counter is used for time.
>>
>> This configuration with uart1 was tested on zcu100-revC.
>>
>> U-Boot 2018.05-rc2-00021-gd058a08d907d (Apr 18 2018 - 14:11:27 +0200)
>>
>> Model: Xilinx ZynqMP R5
>> DRAM: 512 MiB
>> WARNING: Caches not enabled
>> MMC:
>> In: serial at ff010000
>> Out: serial at ff010000
>> Err: serial at ff010000
>> Net: Net Initialization Skipped
>> No ethernet found.
>> ZynqMP r5>
>>
>> There are two ways how to run this on ZynqMP.
>> 1. Run from ZynqMP arm64
>> tftpb 20000000 u-boot-r5.elf
>> setenv autostart no && bootelf -p 20000000
>> cpu 4 disable && cpu 4 release 10000000 lockstep
>> or
>> cpu 4 disable && cpu 4 release 10000000 split
>>
>> 2. Load via jtag when directly to R5
>>
>> Signed-off-by: Michal Simek <michal.simek at xilinx.com>
>> ---
>>
>> MAINTAINERS | 6 +++
>> arch/arm/Kconfig | 16 +++++++
>> arch/arm/Makefile | 1 +
>> arch/arm/cpu/armv7r/Makefile | 4 ++
>> arch/arm/cpu/armv7r/config.mk | 3 ++
>> arch/arm/cpu/armv7r/cpu.c | 24 ++++++++++
>> arch/arm/cpu/armv7r/start.S | 17 +++++++
>> arch/arm/dts/Makefile | 2 +
>> arch/arm/dts/zynqmp-r5.dts | 73 ++++++++++++++++++++++++++++++
>> arch/arm/mach-zynqmp-r5/Kconfig | 27 +++++++++++
>> arch/arm/mach-zynqmp-r5/Makefile | 3 ++
>> arch/arm/mach-zynqmp-r5/cpu.c | 15 ++++++
>> board/xilinx/zynqmp_r5/MAINTAINERS | 7 +++
>> board/xilinx/zynqmp_r5/Makefile | 6 +++
>> board/xilinx/zynqmp_r5/board.c | 25 ++++++++++
>> configs/xilinx_zynqmp_r5_defconfig | 16 +++++++
>> drivers/serial/Kconfig | 2 +-
>> include/configs/xilinx_zynqmp_r5.h | 49 ++++++++++++++++++++
>> 18 files changed, 295 insertions(+), 1 deletion(-)
>> create mode 100644 arch/arm/cpu/armv7r/Makefile
>> create mode 100644 arch/arm/cpu/armv7r/config.mk
>> create mode 100644 arch/arm/cpu/armv7r/cpu.c
>> create mode 100644 arch/arm/cpu/armv7r/start.S
>> create mode 100644 arch/arm/dts/zynqmp-r5.dts
>> create mode 100644 arch/arm/mach-zynqmp-r5/Kconfig
>> create mode 100644 arch/arm/mach-zynqmp-r5/Makefile
>> create mode 100644 arch/arm/mach-zynqmp-r5/cpu.c
>> create mode 100644 board/xilinx/zynqmp_r5/MAINTAINERS
>> create mode 100644 board/xilinx/zynqmp_r5/Makefile
>> create mode 100644 board/xilinx/zynqmp_r5/board.c
>> create mode 100644 configs/xilinx_zynqmp_r5_defconfig
>> create mode 100644 include/configs/xilinx_zynqmp_r5.h
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 76c6f71d6af2..c78a698f75b0 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -293,6 +293,12 @@ F: include/zynqmppl.h
>> F: tools/zynqimage.c
>> N: zynqmp
>> +ARM ZYNQMP R5
>> +M: Michal Simek <michal.simek at xilinx.com>
>> +S: Maintained
>> +T: git git://git.denx.de/u-boot-microblaze.git
>> +F: arch/arm/mach-zynqmp-r5/
>> +
>> BUILDMAN
>> M: Simon Glass <sjg at chromium.org>
>> S: Maintained
>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>> index 7212fc5afa72..c6d8d4d4984d 100644
>> --- a/arch/arm/Kconfig
>> +++ b/arch/arm/Kconfig
>> @@ -192,6 +192,10 @@ config CPU_V7M
>> select THUMB2_KERNEL
>> select SYS_CACHE_SHIFT_5
>> +config CPU_V7R
>> + bool
>> + select SYS_CACHE_SHIFT_6
>
> I think you want to split out Cortex-R support from platform support for
> zynqmp-r5.
R5 support is quite minimal that's why I kept it like this. But I can
split it with no problem.
>
>> +
>> config CPU_PXA
>> bool
>> select SYS_CACHE_SHIFT_5
>> @@ -209,6 +213,7 @@ config SYS_CPU
>> default "arm1176" if CPU_ARM1176
>> default "armv7" if CPU_V7
>> default "armv7m" if CPU_V7M
>> + default "armv7r" if CPU_V7R
>> default "pxa" if CPU_PXA
>> default "sa1100" if CPU_SA1100
>> default "armv8" if ARM64
>> @@ -223,6 +228,7 @@ config SYS_ARM_ARCH
>> default 6 if CPU_ARM1176
>> default 7 if CPU_V7
>> default 7 if CPU_V7M
>> + default 7 if CPU_V7R
>> default 5 if CPU_PXA
>> default 4 if CPU_SA1100
>> default 8 if ARM64
>> @@ -764,6 +770,14 @@ config ARCH_ZYNQ
>> imply FAT_WRITE
>> imply CMD_SPL
>> +config ARCH_ZYNQMP_R5
>> + bool "Xilinx ZynqMP R5 based platform"
>> + select CPU_V7R
>> + select OF_CONTROL
>> + select DM
>> + select DM_SERIAL
>> + select CLK
>> +
>> config ARCH_ZYNQMP
>> bool "Xilinx ZynqMP based platform"
>> select ARM64
>> @@ -1282,6 +1296,8 @@ source "arch/arm/cpu/armv7/vf610/Kconfig"
>> source "arch/arm/mach-zynq/Kconfig"
>> +source "arch/arm/mach-zynqmp-r5/Kconfig"
>> +
>> source "arch/arm/cpu/armv7/Kconfig"
>> source "arch/arm/cpu/armv8/zynqmp/Kconfig"
>> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
>> index 4fa8b38397d9..b4b45f3c6328 100644
>> --- a/arch/arm/Makefile
>> +++ b/arch/arm/Makefile
>> @@ -76,6 +76,7 @@ machine-$(CONFIG_ARCH_STM32MP) += stm32mp
>> machine-$(CONFIG_TEGRA) += tegra
>> machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
>> machine-$(CONFIG_ARCH_ZYNQ) += zynq
>> +machine-$(CONFIG_ARCH_ZYNQMP_R5) += zynqmp-r5
>> machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
>> diff --git a/arch/arm/cpu/armv7r/Makefile
>> b/arch/arm/cpu/armv7r/Makefile
>> new file mode 100644
>> index 000000000000..3c66976dfa62
>> --- /dev/null
>> +++ b/arch/arm/cpu/armv7r/Makefile
>> @@ -0,0 +1,4 @@
>> +# SPDX-License-Identifier: GPL-2.0
>> +
>> +extra-y := start.o
>> +obj-y += cpu.o
>> diff --git a/arch/arm/cpu/armv7r/config.mk
>> b/arch/arm/cpu/armv7r/config.mk
>> new file mode 100644
>> index 000000000000..d365386eb183
>> --- /dev/null
>> +++ b/arch/arm/cpu/armv7r/config.mk
>> @@ -0,0 +1,3 @@
>> +# SPDX-License-Identifier: GPL-2.0
>> +
>> +PLATFORM_CPPFLAGS += -mcpu=cortex-r5 -DARMR5 -mfpu=vfpv3-d16
>
> Are you sure you want to tell gcc about the FPU?
>
>> diff --git a/arch/arm/cpu/armv7r/cpu.c b/arch/arm/cpu/armv7r/cpu.c
>> new file mode 100644
>> index 000000000000..e384a530c5e0
>> --- /dev/null
>> +++ b/arch/arm/cpu/armv7r/cpu.c
>> @@ -0,0 +1,24 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * (C) Copyright 2018 Xilinx, Inc. (Michal Simek)
>> + */
>> +
>> +#include <common.h>
>> +
>> +/*
>> + * This is called right before passing control to
>> + * the Linux kernel point.
>> + */
>> +int cleanup_before_linux(void)
>> +{
>> + return 0;
>> +}
>> +
>> +/*
>> + * Perform the low-level reset.
>> + */
>> +void reset_cpu(ulong addr)
>> +{
>> + while (1)
>> + ;
>
> If the R5 is your main U-Boot provider, this should do something
> different ;). But that can come later.
It is really minimal support to enable others to play with it.
At this stage this is not important.
>> +}
>> diff --git a/arch/arm/cpu/armv7r/start.S b/arch/arm/cpu/armv7r/start.S
>> new file mode 100644
>> index 000000000000..d6e8eecf54b7
>> --- /dev/null
>> +++ b/arch/arm/cpu/armv7r/start.S
>> @@ -0,0 +1,17 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * (C) Copyright 2015
>> + * Kamil Lulko, <kamil.lulko at gmail.com>
>> + *
>> + */
>> +
>> +#include <asm/assembler.h>
>> +
>> +.globl reset
>> +.type reset, %function
>> +reset:
>> + W(b) _main
>> +
>> +.globl c_runtime_cpu_setup
>> +c_runtime_cpu_setup:
>> + mov pc, lr
>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>> index e11c41da0156..e38184869a1c 100644
>> --- a/arch/arm/dts/Makefile
>> +++ b/arch/arm/dts/Makefile
>> @@ -165,6 +165,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
>> zynqmp-zc1751-xm017-dc3.dtb \
>> zynqmp-zc1751-xm018-dc4.dtb \
>> zynqmp-zc1751-xm019-dc5.dtb
>> +dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \
>> + zynqmp-r5.dtb
>
> I would expect that people will eventually want to use CONFIG_OF_BOARD
> and a device tree passed in from the main core / at a hard coded location.
I am using OF_EMBED right now to get something working via jtag or
boot.bin which expects elf files. Different configurations are possible
but not tested right now.
>> dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \
>> am335x-draco.dtb \
>> am335x-evm.dtb \
>> diff --git a/arch/arm/dts/zynqmp-r5.dts b/arch/arm/dts/zynqmp-r5.dts
>> new file mode 100644
>> index 000000000000..ba4d66a167c2
>> --- /dev/null
>> +++ b/arch/arm/dts/zynqmp-r5.dts
>> @@ -0,0 +1,73 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * dts file for Xilinx ZynqMP R5
>> + *
>> + * (C) Copyright 2018, Xilinx, Inc.
>> + *
>> + * Michal Simek <michal.simek at xilinx.com>
>> + */
>> +
>> +/dts-v1/;
>> +
>> +/ {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + compatible = "xlnx,zynqmp-r5";
>> + model = "Xilinx ZynqMP R5";
>> +
>> + cpus {
>> + #address-cells = <0x1>;
>> + #size-cells = <0x0>;
>> +
>> + cpu at 0 {
>> + compatible = "arm,cortex-r5";
>> + device_type = "cpu";
>> + reg = <0>;
>> + };
>> + };
>> +
>> + aliases {
>> + serial0 = &uart1;
>> + };
>> +
>> + memory at 0 {
>> + device_type = "memory";
>> + reg = <0x10000000 0x20000000>;
>> + };
>> +
>> + chosen {
>> + bootargs = "";
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + clk100: clk100 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <100000000>;
>> + u-boot,dm-pre-reloc;
>> + };
>> +
>> + amba {
>> + u-boot,dm-pre-reloc;
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + ttc0: timer at ff110000 {
>> + compatible = "cdns,ttc";
>> + status = "okay";
>> + reg = <0xff110000 0x1000>;
>> + timer-width = <32>;
>> + clocks = <&clk100>;
>> + };
>> +
>> + uart1: serial at ff010000 {
>> + u-boot,dm-pre-reloc;
>> + compatible = "cdns,uart-r1p12", "xlnx,xuartps";
>> + reg = <0xff010000 0x1000>;
>> + clock-names = "uart_clk", "pclk";
>> + clocks = <&clk100 &clk100>;
>> + };
>> + };
>> +};
>> diff --git a/arch/arm/mach-zynqmp-r5/Kconfig
>> b/arch/arm/mach-zynqmp-r5/Kconfig
>> new file mode 100644
>> index 000000000000..5e0175413395
>> --- /dev/null
>> +++ b/arch/arm/mach-zynqmp-r5/Kconfig
>> @@ -0,0 +1,27 @@
>> +# SPDX-License-Identifier: GPL-2.0
>> +
>> +if ARCH_ZYNQMP_R5
>> +
>> +config SYS_BOARD
>> + string "Board name"
>> + default "zynqmp_r5"
>> +
>> +config SYS_VENDOR
>> + string "Vendor name"
>> + default "xilinx"
>> +
>> +config SYS_SOC
>> + default "zynqmp-r5"
>> +
>> +config SYS_CONFIG_NAME
>> + string "Board configuration name"
>> + default "xilinx_zynqmp_r5"
>> + help
>> + This option contains information about board configuration name.
>> + Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h
>> header
>> + will be used for board configuration.
>> +
>> +config SYS_MALLOC_F_LEN
>> + default 0x600
>> +
>> +endif
>> diff --git a/arch/arm/mach-zynqmp-r5/Makefile
>> b/arch/arm/mach-zynqmp-r5/Makefile
>> new file mode 100644
>> index 000000000000..0d39e97dd371
>> --- /dev/null
>> +++ b/arch/arm/mach-zynqmp-r5/Makefile
>> @@ -0,0 +1,3 @@
>> +# SPDX-License-Identifier: GPL-2.0
>> +
>> +obj-y += cpu.o
>> diff --git a/arch/arm/mach-zynqmp-r5/cpu.c
>> b/arch/arm/mach-zynqmp-r5/cpu.c
>> new file mode 100644
>> index 000000000000..0d86e2d1c886
>> --- /dev/null
>> +++ b/arch/arm/mach-zynqmp-r5/cpu.c
>> @@ -0,0 +1,15 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2018 Xilinx, Inc. (Michal Simek)
>> + */
>> +
>> +#include <common.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +int arch_cpu_init(void)
>> +{
>> + gd->cpu_clk = CONFIG_CPU_FREQ_HZ;
>> +
>> + return 0;
>> +}
>> diff --git a/board/xilinx/zynqmp_r5/MAINTAINERS
>> b/board/xilinx/zynqmp_r5/MAINTAINERS
>> new file mode 100644
>> index 000000000000..ac267649781a
>> --- /dev/null
>> +++ b/board/xilinx/zynqmp_r5/MAINTAINERS
>> @@ -0,0 +1,7 @@
>> +XILINX_ZYNQMP_R5 BOARDS
>> +M: Michal Simek <michal.simek at xilinx.com>
>> +S: Maintained
>> +F: arch/arm/dts/zynqmp-r5*
>> +F: board/xilinx/zynqmp_r5/
>> +F: include/configs/xilinx_zynqmp_r5_*
>> +F: configs/xilinx_zynqmp_r5_*
>> diff --git a/board/xilinx/zynqmp_r5/Makefile
>> b/board/xilinx/zynqmp_r5/Makefile
>> new file mode 100644
>> index 000000000000..c5a3e3d328bd
>> --- /dev/null
>> +++ b/board/xilinx/zynqmp_r5/Makefile
>> @@ -0,0 +1,6 @@
>> +# SPDX-License-Identifier: GPL-2.0
>> +#
>> +# (C) Copyright 2018 Xilinx, Inc. (Michal Simek)
>> +#
>> +
>> +obj-y := board.o
>> diff --git a/board/xilinx/zynqmp_r5/board.c
>> b/board/xilinx/zynqmp_r5/board.c
>> new file mode 100644
>> index 000000000000..70fb20235498
>> --- /dev/null
>> +++ b/board/xilinx/zynqmp_r5/board.c
>> @@ -0,0 +1,25 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * (C) Copyright 2018 Xilinx, Inc. (Michal Simek)
>> + */
>> +
>> +#include <common.h>
>> +#include <fdtdec.h>
>> +
>> +int board_init(void)
>> +{
>> + return 0;
>> +}
>> +
>> +int dram_init_banksize(void)
>> +{
>> + return fdtdec_setup_memory_banksize();
>> +}
>> +
>> +int dram_init(void)
>> +{
>> + if (fdtdec_setup_memory_size() != 0)
>> + return -EINVAL;
>> +
>> + return 0;
>> +}
>> diff --git a/configs/xilinx_zynqmp_r5_defconfig
>> b/configs/xilinx_zynqmp_r5_defconfig
>> new file mode 100644
>> index 000000000000..46715242e703
>> --- /dev/null
>> +++ b/configs/xilinx_zynqmp_r5_defconfig
>> @@ -0,0 +1,16 @@
>> +CONFIG_ARM=y
>> +CONFIG_ARCH_ZYNQMP_R5=y
>> +CONFIG_SYS_TEXT_BASE=0x10000000
>
> You may want to document somewhere what this address is. Is this OCM? Is
> this DDR? Is this the super-fast local RAM of the R5?
In commit message it is written about DDR but maybe it can be more
explicitly said.
>> +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-r5"
>> +CONFIG_DEBUG_UART=y
>> +# CONFIG_DISPLAY_CPUINFO is not set
>> +CONFIG_SYS_PROMPT="ZynqMP r5> "
>> +# CONFIG_CMD_FLASH is not set
>> +# CONFIG_CMD_SETEXPR is not set
>> +CONFIG_OF_EMBED=y
>> +CONFIG_DEBUG_UART_ZYNQ=y
>> +CONFIG_DEBUG_UART_BASE=0xff010000
>> +CONFIG_DEBUG_UART_CLOCK=100000000
>> +CONFIG_ZYNQ_SERIAL=y
>> +CONFIG_TIMER=y
>> +CONFIG_CADENCE_TTC_TIMER=y
>> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
>> index 3d5b2bf15f08..3292edbaf240 100644
>> --- a/drivers/serial/Kconfig
>> +++ b/drivers/serial/Kconfig
>> @@ -617,7 +617,7 @@ config STM32_SERIAL
>> config ZYNQ_SERIAL
>> bool "Cadence (Xilinx Zynq) UART support"
>> - depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
>> + depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP
>> || ARCH_ZYNQMP_R5)
>
> I'm sure there are more drivers that could be accessed from the R5
> instead, right?
I would expect that but it needs to be tested which is not at this
stage. This is minimal support with DDR/timer/serial which is enough for
now.
>
> Either way, I'm happy to see this port - looks like great work :)
Happy to see any your tag to write it to the history.
Cheers,
Michal
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