[U-Boot] [RFC PATCH 5/5] arm: v7R: Add support for enabling caches

[Lokesh Vutla]

Cache maintenance procedure is same for v7 and v7R
processors. So re-use cache-cp15.c file except for
mmu parts.

Signed-off-by: Lokesh Vutla <lokeshvutla at ti.com>
---
 arch/arm/cpu/armv7/mpu_v7r.c | 11 +++++++++++
 arch/arm/lib/Makefile        |  3 +++
 arch/arm/lib/cache-cp15.c    | 14 +++++++++++++-
 3 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/mpu_v7r.c b/arch/arm/cpu/armv7/mpu_v7r.c
index 703f744b31..b998ab9320 100644
--- a/arch/arm/cpu/armv7/mpu_v7r.c
+++ b/arch/arm/cpu/armv7/mpu_v7r.c
@@ -107,3 +107,14 @@ void setup_mpu_regions(struct mpu_region_config *rgns, u32 num_rgns)
 
 	icache_enable();
 }
+
+void enable_caches(void)
+{
+	/*
+	 * setup_mpu_regions() might have enabled Icache. So add a check
+	 * before enabling Icache
+	 */
+	if (!icache_status())
+		icache_enable();
+	dcache_enable();
+}
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index f907adc161..f8377ba18a 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -64,6 +64,9 @@ endif
 
 obj-y	+= cache.o
 obj-$(CONFIG_MMU)	+= cache-cp15.o
+ifeq ($(CONFIG_CPU_V7R)$(CONFIG_ARM_MPU),yy)
+obj-y	+= cache-cp15.o
+endif
 
 obj-y	+= psci-dt.o
 
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index f0c1b03728..fea7d3fdec 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -9,11 +9,15 @@
 #include <asm/system.h>
 #include <asm/cache.h>
 #include <linux/compiler.h>
+#ifdef CONFIG_ARM_MPU
+#include <asm/armv7m_mpu.h>
+#endif
 
 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_MMU
 __weak void arm_init_before_mmu(void)
 {
 }
@@ -202,15 +206,23 @@ static int mmu_enabled(void)
 {
 	return get_cr() & CR_M;
 }
+#endif /* CONFIG_MMU */
 
 /* cache_bit must be either CR_I or CR_C */
 static void cache_enable(uint32_t cache_bit)
 {
 	uint32_t reg;
 
-	/* The data cache is not active unless the mmu is enabled too */
+	/* The data cache is not active unless the mmu/mpu is enabled too */
+#ifdef CONFIG_MMU
 	if ((cache_bit == CR_C) && !mmu_enabled())
 		mmu_setup();
+#elif defined(CONFIG_ARM_MPU)
+	if ((cache_bit == CR_C) && !mpu_enabled()) {
+		printf("Consider enabling MPU before enabling caches\n");
+		return;
+	}
+#endif
 	reg = get_cr();	/* get control reg. */
 	set_cr(reg | cache_bit);
 }
-- 
2.17.0