[U-Boot] [PATCH 2/3] sunxi: sun8i: Add Allwinner V40 support
Jagan Teki
jagan at amarulasolutions.com
Wed Apr 25 09:50:14 UTC 2018
Allwinner V40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU,
and a Mali400 MP2 GPU from ARM. It is the automotive version of R40.
This patch add support for V40 by reusing R40 configurations.
MACH_SUN8I_R40_V40 is the common config option for both.
Also fixed checkpatch warnings while making these changes.
Signed-off-by: Jagan Teki <jagan at amarulasolutions.com>
---
arch/arm/cpu/armv7/sunxi/psci.c | 10 ++++----
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 4 +--
arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 6 ++---
arch/arm/include/asm/arch-sunxi/timer.h | 2 +-
arch/arm/include/asm/arch-sunxi/watchdog.h | 6 ++---
arch/arm/mach-sunxi/Kconfig | 36 ++++++++++++++++-----------
arch/arm/mach-sunxi/board.c | 11 ++++----
arch/arm/mach-sunxi/clock_sun6i.c | 9 +++----
arch/arm/mach-sunxi/cpu_info.c | 2 ++
arch/arm/mach-sunxi/dram_sunxi_dw.c | 6 ++---
arch/arm/mach-sunxi/pmic_bus.c | 8 +++---
board/sunxi/board.c | 26 ++++++++-----------
drivers/power/Kconfig | 18 +++++++-------
13 files changed, 74 insertions(+), 70 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
index 18da9cb864..39195b6313 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.c
+++ b/arch/arm/cpu/armv7/sunxi/psci.c
@@ -80,7 +80,7 @@ static void __secure clamp_release(u32 __maybe_unused *clamp)
{
#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_H3) || \
- defined(CONFIG_MACH_SUN8I_R40)
+ defined(CONFIG_MACH_SUN8I_R40_V40)
u32 tmp = 0x1ff;
do {
tmp >>= 1;
@@ -95,7 +95,7 @@ static void __secure clamp_set(u32 __maybe_unused *clamp)
{
#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_H3) || \
- defined(CONFIG_MACH_SUN8I_R40)
+ defined(CONFIG_MACH_SUN8I_R40_V40)
writel(0xff, clamp);
#endif
}
@@ -118,7 +118,7 @@ static void __secure sunxi_power_switch(u32 *clamp, u32 *pwroff, bool on,
}
}
-#ifdef CONFIG_MACH_SUN8I_R40
+#ifdef CONFIG_MACH_SUN8I_R40_V40
/* secondary core entry address is programmed differently on R40 */
static void __secure sunxi_set_entry_address(void *entry)
{
@@ -145,7 +145,7 @@ static void __secure sunxi_cpu_set_power(int __always_unused cpu, bool on)
sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff,
on, 0);
}
-#elif defined CONFIG_MACH_SUN8I_R40
+#elif defined CONFIG_MACH_SUN8I_R40_V40
static void __secure sunxi_cpu_set_power(int cpu, bool on)
{
struct sunxi_cpucfg_reg *cpucfg =
@@ -155,7 +155,7 @@ static void __secure sunxi_cpu_set_power(int cpu, bool on)
(void *)cpucfg + SUN8I_R40_PWROFF,
on, 0);
}
-#else /* ! CONFIG_MACH_SUN7I && ! CONFIG_MACH_SUN8I_R40 */
+#else /* ! CONFIG_MACH_SUN7I && ! CONFIG_MACH_SUN8I_R40_V40 */
static void __secure sunxi_cpu_set_power(int cpu, bool on)
{
struct sunxi_prcm_reg *prcm =
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index d35aa479f7..c4d8c58716 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -285,7 +285,7 @@ struct sunxi_ccm_reg {
#define AHB_GATE_OFFSET_USB_EHCI1 27
#define AHB_GATE_OFFSET_USB_EHCI0 26
#endif
-#ifndef CONFIG_MACH_SUN8I_R40
+#ifndef CONFIG_MACH_SUN8I_R40_V40
#define AHB_GATE_OFFSET_USB0 24
#else
#define AHB_GATE_OFFSET_USB0 25
@@ -439,7 +439,7 @@ struct sunxi_ccm_reg {
#define CCM_PLL11_PATTERN 0xf5860000
/* ahb_reset0 offsets */
-#ifdef CONFIG_MACH_SUN8I_R40
+#ifdef CONFIG_MACH_SUN8I_R40_V40
#define AHB_RESET_OFFSET_SATA 24
#endif
#define AHB_RESET_OFFSET_GMAC 17
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index 2419062d45..89300064e1 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -114,7 +114,7 @@ defined(CONFIG_MACH_SUN50I)
#define SUNXI_TP_BASE 0x01c25000
#define SUNXI_PMU_BASE 0x01c25400
-#if defined CONFIG_MACH_SUN7I || defined CONFIG_MACH_SUN8I_R40
+#if defined CONFIG_MACH_SUN7I || defined CONFIG_MACH_SUN8I_R40_V40
#define SUNXI_CPUCFG_BASE 0x01c25c00
#endif
@@ -186,8 +186,8 @@ defined(CONFIG_MACH_SUN50I)
#define SUNXI_PRCM_BASE 0x01f01400
#if defined CONFIG_SUNXI_GEN_SUN6I && \
- !defined CONFIG_MACH_SUN8I_A83T && \
- !defined CONFIG_MACH_SUN8I_R40
+ !defined CONFIG_MACH_SUN8I_A83T && \
+ !defined CONFIG_MACH_SUN8I_R40_V40
#define SUNXI_CPUCFG_BASE 0x01f01c00
#endif
diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h
index ccdf942534..de1a5c1e83 100644
--- a/arch/arm/include/asm/arch-sunxi/timer.h
+++ b/arch/arm/include/asm/arch-sunxi/timer.h
@@ -67,7 +67,7 @@ struct sunxi_timer_reg {
struct sunxi_timer timer[6]; /* We have 6 timers */
u8 res2[16];
struct sunxi_avs avs;
-#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
+#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40_V40)
struct sunxi_wdog wdog; /* 0x90 */
/* XXX the following is not accurate for sun5i/sun7i */
struct sunxi_64cnt cnt64; /* 0xa0 */
diff --git a/arch/arm/include/asm/arch-sunxi/watchdog.h b/arch/arm/include/asm/arch-sunxi/watchdog.h
index ce6d664856..a1041c00c8 100644
--- a/arch/arm/include/asm/arch-sunxi/watchdog.h
+++ b/arch/arm/include/asm/arch-sunxi/watchdog.h
@@ -14,9 +14,9 @@
#define WDT_CTRL_KEY (0x0a57 << 1)
#if defined(CONFIG_MACH_SUN4I) || \
- defined(CONFIG_MACH_SUN5I) || \
- defined(CONFIG_MACH_SUN7I) || \
- defined(CONFIG_MACH_SUN8I_R40)
+ defined(CONFIG_MACH_SUN5I) || \
+ defined(CONFIG_MACH_SUN7I) || \
+ defined(CONFIG_MACH_SUN8I_R40_V40)
#define WDT_MODE_EN (0x1 << 0)
#define WDT_MODE_RESET_EN (0x1 << 1)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index b868f0e350..c50642e1b4 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -121,6 +121,17 @@ config SUNXI_DRAM_DW_32BIT
32-bit memory buswidth.
endif
+config MACH_SUN8I_R40_V40
+ bool
+ select CPU_V7
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
+ select ARCH_SUPPORT_PSCI
+ select SUNXI_GEN_SUN6I
+ select SUPPORT_SPL
+ select SUNXI_DRAM_DW
+ select SUNXI_DRAM_DW_32BIT
+
config MACH_SUNXI_H3_H5
bool
select DM_I2C
@@ -218,14 +229,7 @@ config MACH_SUN8I_H3
config MACH_SUN8I_R40
bool "sun8i (Allwinner R40)"
- select CPU_V7
- select CPU_V7_HAS_NONSEC
- select CPU_V7_HAS_VIRT
- select ARCH_SUPPORT_PSCI
- select SUNXI_GEN_SUN6I
- select SUPPORT_SPL
- select SUNXI_DRAM_DW
- select SUNXI_DRAM_DW_32BIT
+ select MACH_SUN8I_R40_V40
config MACH_SUN8I_V3S
bool "sun8i (Allwinner V3s)"
@@ -239,6 +243,10 @@ config MACH_SUN8I_V3S
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+config MACH_SUN8I_V40
+ bool "sun8i (Allwinner V40)"
+ select MACH_SUN8I_R40_V40
+
config MACH_SUN9I
bool "sun9i (Allwinner A80)"
select CPU_V7
@@ -281,7 +289,7 @@ config MACH_SUN8I
default y if MACH_SUN8I_A33
default y if MACH_SUN8I_A83T
default y if MACH_SUNXI_H3_H5
- default y if MACH_SUN8I_R40
+ default y if MACH_SUN8I_R40_V40
default y if MACH_SUN8I_V3S
config RESERVE_ALLWINNER_BOOT0_HEADER
@@ -358,7 +366,7 @@ config DRAM_TYPE
config DRAM_CLK
int "sunxi dram clock speed"
default 792 if MACH_SUN9I
- default 648 if MACH_SUN8I_R40
+ default 648 if MACH_SUN8I_R40_V40
default 312 if MACH_SUN6I || MACH_SUN8I
default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
MACH_SUN8I_V3S
@@ -382,7 +390,7 @@ config DRAM_ZQ
default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
default 127 if MACH_SUN7I
default 14779 if MACH_SUN8I_V3S
- default 3881979 if MACH_SUN8I_R40
+ default 3881979 if MACH_SUN8I_R40_V40
default 4145117 if MACH_SUN9I
default 3881915 if MACH_SUN50I
---help---
@@ -392,7 +400,7 @@ config DRAM_ODT_EN
bool "sunxi dram odt enable"
default n if !MACH_SUN8I_A23
default y if MACH_SUN8I_A23
- default y if MACH_SUN8I_R40
+ default y if MACH_SUN8I_R40_V40
default y if MACH_SUN50I
---help---
Select this to enable dram odt (on die termination).
@@ -633,7 +641,7 @@ config USB3_VBUS_PIN
config I2C0_ENABLE
bool "Enable I2C/TWI controller 0"
- default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
+ default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40_V40
default n if MACH_SUN6I || MACH_SUN8I
select CMD_I2C
---help---
@@ -694,7 +702,7 @@ config VIDEO_SUNXI
bool "Enable graphical uboot console on HDMI, LCD or VGA"
depends on !MACH_SUN8I_A83T
depends on !MACH_SUNXI_H3_H5
- depends on !MACH_SUN8I_R40
+ depends on !MACH_SUN8I_R40_V40
depends on !MACH_SUN8I_V3S
depends on !MACH_SUN9I
depends on !MACH_SUN50I
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 1753faec1d..8e097d67e6 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -67,14 +67,13 @@ struct mm_region *mem_map = sunxi_mem_map;
static int gpio_init(void)
{
#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
-#if defined(CONFIG_MACH_SUN4I) || \
- defined(CONFIG_MACH_SUN7I) || \
- defined(CONFIG_MACH_SUN8I_R40)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
+ defined(CONFIG_MACH_SUN8I_R40_V40)
/* disable GPB22,23 as uart0 tx,rx to avoid conflict */
sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
#endif
-#if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
+#if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40_V40)
sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
#else
@@ -84,7 +83,7 @@ static int gpio_init(void)
sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
defined(CONFIG_MACH_SUN7I) || \
- defined(CONFIG_MACH_SUN8I_R40))
+ defined(CONFIG_MACH_SUN8I_R40_V40))
sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
@@ -275,7 +274,7 @@ void board_init_f(ulong dummy)
void reset_cpu(ulong addr)
{
-#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
+#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40_V40)
static const struct sunxi_wdog *wdog =
&((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
index 870ff5b1e0..6347085a76 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -35,7 +35,7 @@ void clock_init_safe(void)
clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
#endif
-#if defined(CONFIG_MACH_SUN8I_R40) || defined(CONFIG_MACH_SUN50I)
+#if defined(CONFIG_MACH_SUN8I_R40_V40) || defined(CONFIG_MACH_SUN50I)
/* Set PLL lock enable bits and switch to old lock mode */
writel(GENMASK(12, 0), &ccm->pll_lock_ctrl);
#endif
@@ -52,7 +52,7 @@ void clock_init_safe(void)
if (IS_ENABLED(CONFIG_MACH_SUN6I))
writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
-#if defined(CONFIG_MACH_SUN8I_R40) && defined(CONFIG_SUNXI_AHCI)
+#if defined(CONFIG_MACH_SUN8I_R40_V40) && defined(CONFIG_SUNXI_AHCI)
setbits_le32(&ccm->sata_pll_cfg, CCM_SATA_PLL_DEFAULT);
setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_GATE_OFFSET_SATA);
setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);
@@ -273,9 +273,8 @@ void clock_set_pll10(unsigned int clk)
}
#endif
-#if defined(CONFIG_MACH_SUN8I_A33) || \
- defined(CONFIG_MACH_SUN8I_R40) || \
- defined(CONFIG_MACH_SUN50I)
+#if defined(CONFIG_MACH_SUN8I_A33) || defined(CONFIG_MACH_SUN8I_R40_V40) || \
+ defined(CONFIG_MACH_SUN50I)
void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
{
struct sunxi_ccm_reg * const ccm =
diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
index 25a5ec26a0..6f1386b2d0 100644
--- a/arch/arm/mach-sunxi/cpu_info.c
+++ b/arch/arm/mach-sunxi/cpu_info.c
@@ -89,6 +89,8 @@ int print_cpuinfo(void)
printf("CPU: Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id());
#elif defined CONFIG_MACH_SUN8I_R40
printf("CPU: Allwinner R40 (SUN8I %04x)\n", sunxi_get_sram_id());
+#elif defined CONFIG_MACH_SUN8I_V40
+ printf("CPU: Allwinner V40 (SUN8I %04x)\n", sunxi_get_sram_id());
#elif defined CONFIG_MACH_SUN8I_V3S
printf("CPU: Allwinner V3s (SUN8I %04x)\n", sunxi_get_sram_id());
#elif defined CONFIG_MACH_SUN9I
diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c
index 78b4ffb9c3..ffe39216c7 100644
--- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
+++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
@@ -43,7 +43,7 @@ static void mctl_set_bit_delays(struct dram_para *para)
writel(ACBDLR_WRITE_DELAY(para->ac_delays[i]),
&mctl_ctl->acbdlr[i]);
-#ifdef CONFIG_MACH_SUN8I_R40
+#ifdef CONFIG_MACH_SUN8I_R40_V40
/* DQSn, DMn, DQn output enable bit delay */
for (i = 0; i < 4; i++)
writel(0x6 << 24, &mctl_ctl->dx[i].sdlr);
@@ -700,7 +700,7 @@ unsigned long sunxi_dram_init(void)
.dx_read_delays = SUN8I_H3_DX_READ_DELAYS,
.dx_write_delays = SUN8I_H3_DX_WRITE_DELAYS,
.ac_delays = SUN8I_H3_AC_DELAYS,
-#elif defined(CONFIG_MACH_SUN8I_R40)
+#elif defined(CONFIG_MACH_SUN8I_R40_V40)
.dx_read_delays = SUN8I_R40_DX_READ_DELAYS,
.dx_write_delays = SUN8I_R40_DX_WRITE_DELAYS,
.ac_delays = SUN8I_R40_AC_DELAYS,
@@ -721,7 +721,7 @@ unsigned long sunxi_dram_init(void)
*/
#if defined(CONFIG_MACH_SUN8I_H3)
uint16_t socid = SOCID_H3;
-#elif defined(CONFIG_MACH_SUN8I_R40)
+#elif defined(CONFIG_MACH_SUN8I_R40_V40)
uint16_t socid = SOCID_R40;
/* Currently we cannot support R40 with dual rank memory */
para.dual_rank = 0;
diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c
index f917c3e070..5f48bb1942 100644
--- a/arch/arm/mach-sunxi/pmic_bus.c
+++ b/arch/arm/mach-sunxi/pmic_bus.c
@@ -41,8 +41,8 @@ int pmic_bus_init(void)
p2wi_init();
ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
AXP221_INIT_DATA);
-# elif defined CONFIG_MACH_SUN8I_R40
- /* Nothing. R40 uses the AXP221s in I2C mode */
+# elif defined CONFIG_MACH_SUN8I_R40_V40
+ /* Nothing. R40_V40 uses the AXP221s in I2C mode */
ret = 0;
# else
ret = rsb_init();
@@ -68,7 +68,7 @@ int pmic_bus_read(u8 reg, u8 *data)
#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
# ifdef CONFIG_MACH_SUN6I
return p2wi_read(reg, data);
-# elif defined CONFIG_MACH_SUN8I_R40
+# elif defined CONFIG_MACH_SUN8I_R40_V40
return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1);
# else
return rsb_read(AXP223_RUNTIME_ADDR, reg, data);
@@ -85,7 +85,7 @@ int pmic_bus_write(u8 reg, u8 data)
#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
# ifdef CONFIG_MACH_SUN6I
return p2wi_write(reg, data);
-# elif defined CONFIG_MACH_SUN8I_R40
+# elif defined CONFIG_MACH_SUN8I_R40_V40
return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1);
# else
return rsb_write(AXP223_RUNTIME_ADDR, reg, data);
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 322dd9e23a..13fedc29f5 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -82,10 +82,8 @@ DECLARE_GLOBAL_DATA_PTR;
void i2c_init_board(void)
{
#ifdef CONFIG_I2C0_ENABLE
-#if defined(CONFIG_MACH_SUN4I) || \
- defined(CONFIG_MACH_SUN5I) || \
- defined(CONFIG_MACH_SUN7I) || \
- defined(CONFIG_MACH_SUN8I_R40)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || \
+ defined(CONFIG_MACH_SUN7I) || defined(CONFIG_MACH_SUN8I_R40_V40)
sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
clock_twi_onoff(0, 1);
@@ -101,9 +99,8 @@ void i2c_init_board(void)
#endif
#ifdef CONFIG_I2C1_ENABLE
-#if defined(CONFIG_MACH_SUN4I) || \
- defined(CONFIG_MACH_SUN7I) || \
- defined(CONFIG_MACH_SUN8I_R40)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
+ defined(CONFIG_MACH_SUN8I_R40_V40)
sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
clock_twi_onoff(1, 1);
@@ -123,9 +120,8 @@ void i2c_init_board(void)
#endif
#ifdef CONFIG_I2C2_ENABLE
-#if defined(CONFIG_MACH_SUN4I) || \
- defined(CONFIG_MACH_SUN7I) || \
- defined(CONFIG_MACH_SUN8I_R40)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
+ defined(CONFIG_MACH_SUN8I_R40_V40)
sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
clock_twi_onoff(2, 1);
@@ -150,7 +146,7 @@ void i2c_init_board(void)
sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
clock_twi_onoff(3, 1);
#elif defined(CONFIG_MACH_SUN7I) || \
- defined(CONFIG_MACH_SUN8I_R40)
+ defined(CONFIG_MACH_SUN8I_R40_V40)
sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
clock_twi_onoff(3, 1);
@@ -159,7 +155,7 @@ void i2c_init_board(void)
#ifdef CONFIG_I2C4_ENABLE
#if defined(CONFIG_MACH_SUN7I) || \
- defined(CONFIG_MACH_SUN8I_R40)
+ defined(CONFIG_MACH_SUN8I_R40_V40)
sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
clock_twi_onoff(4, 1);
@@ -323,7 +319,7 @@ static void mmc_pinmux_setup(int sdc)
pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
- defined(CONFIG_MACH_SUN8I_R40)
+ defined(CONFIG_MACH_SUN8I_R40_V40)
if (pins == SUNXI_GPIO_H) {
/* SDC1: PH22-PH-27 */
for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
@@ -418,7 +414,7 @@ static void mmc_pinmux_setup(int sdc)
sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
}
-#elif defined(CONFIG_MACH_SUN8I_R40)
+#elif defined(CONFIG_MACH_SUN8I_R40_V40)
/* SDC2: PC6-PC15, PC24 */
for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
@@ -456,7 +452,7 @@ static void mmc_pinmux_setup(int sdc)
pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
- defined(CONFIG_MACH_SUN8I_R40)
+ defined(CONFIG_MACH_SUN8I_R40_V40)
/* SDC3: PI4-PI9 */
for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 1a3852442a..4494075394 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -10,7 +10,7 @@ choice
prompt "Select Sunxi PMIC Variant"
depends on ARCH_SUNXI
default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
- default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40
+ default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40_V40
default AXP818_POWER if MACH_SUN8I_A83T
default SUNXI_NO_PMIC if MACH_SUNXI_H3_H5 || MACH_SUN50I
@@ -39,7 +39,7 @@ config AXP209_POWER
config AXP221_POWER
bool "axp221 / axp223 pmic support"
- depends on MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40
+ depends on MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40_V40
select AXP_PMIC_BUS
select CMD_POWEROFF
---help---
@@ -75,7 +75,7 @@ endchoice
config AXP_DCDC1_VOLT
int "axp pmic dcdc1 voltage"
depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
- default 3300 if AXP818_POWER || MACH_SUN8I_R40
+ default 3300 if AXP818_POWER || MACH_SUN8I_R40_V40
default 3000 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I
---help---
Set the voltage (mV) to program the axp pmic dcdc1 at, set to 0 to
@@ -102,7 +102,7 @@ config AXP_DCDC2_VOLT
On A23/A33 boards dcdc2 is used for VDD-SYS and should be 1.1V.
On A80 boards dcdc2 powers the GPU and can be left off.
On A83T boards dcdc2 is used for VDD-CPUA(cluster 0) and should be 0.9V.
- On R40 boards dcdc2 is VDD-CPU and should be 1.1V
+ On R40_V40 boards dcdc2 is VDD-CPU and should be 1.1V
config AXP_DCDC3_VOLT
int "axp pmic dcdc3 voltage"
@@ -110,7 +110,7 @@ config AXP_DCDC3_VOLT
default 900 if AXP809_POWER || AXP818_POWER
default 1500 if AXP152_POWER
default 1250 if AXP209_POWER
- default 1100 if MACH_SUN8I_R40
+ default 1100 if MACH_SUN8I_R40_V40
default 1200 if MACH_SUN6I || MACH_SUN8I
---help---
Set the voltage (mV) to program the axp pmic dcdc3 at, set to 0 to
@@ -121,7 +121,7 @@ config AXP_DCDC3_VOLT
On A23 / A31 / A33 boards dcdc3 is VDD-CPU and should be 1.2V.
On A80 boards dcdc3 is used for VDD-CPUA(cluster 0) and should be 0.9V.
On A83T boards dcdc3 is used for VDD-CPUB(cluster 1) and should be 0.9V.
- On R40 boards dcdc3 is VDD-SYS and VDD-GPU and should be 1.1V.
+ On R40_V40 boards dcdc3 is VDD-SYS and VDD-GPU and should be 1.1V.
config AXP_DCDC4_VOLT
int "axp pmic dcdc4 voltage"
@@ -146,13 +146,13 @@ config AXP_DCDC5_VOLT
---help---
Set the voltage (mV) to program the axp pmic dcdc5 at, set to 0 to
disable dcdc5.
- On A23 / A31 / A33 / A80 / A83T / R40 boards dcdc5 is VCC-DRAM and
+ On A23 / A31 / A33 / A80 / A83T / R40_V40 boards dcdc5 is VCC-DRAM and
should be 1.5V, 1.35V if DDR3L is used.
config AXP_ALDO1_VOLT
int "axp pmic (a)ldo1 voltage"
depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
- default 0 if MACH_SUN6I || MACH_SUN8I_R40
+ default 0 if MACH_SUN6I || MACH_SUN8I_R40_V40
default 1800 if MACH_SUN8I_A83T
default 3000 if MACH_SUN8I || MACH_SUN9I
---help---
@@ -191,7 +191,7 @@ config AXP_ALDO3_VOLT
Set the voltage (mV) to program the axp pmic aldo3 at, set to 0 to
disable aldo3.
On A10(s) / A13 / A20 boards aldo3 should be 2.8V.
- On A23 / A31 / A33 / R40 boards aldo3 is VCC-PLL and AVCC and should
+ On A23 / A31 / A33 / R40_V40 boards aldo3 is VCC-PLL and AVCC and should
be 3.0V.
On A80 boards aldo3 is normally not used.
On A83T / H8 boards aldo3 is AVCC, VCC-PL, and VCC-LED, and should be
--
2.14.3
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