[U-Boot] [PATCH v7 8/8] armv8: ls1046a: setup SEC ICIDs and fix up device tree

[laurentiu.tudor at nxp.com]

From: Laurentiu Tudor <laurentiu.tudor at nxp.com>

Add support for SEC ICID configuration and apply it for ls1046a.
Also add code to make the necessary device tree fixups.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor at nxp.com>
---
 .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 14 +++++++++++
 .../asm/arch-fsl-layerscape/fsl_icid.h        | 25 +++++++++++++++++++
 .../asm/arch-fsl-layerscape/immap_lsch2.h     |  8 ++++++
 3 files changed, 47 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
index 30c7d8d28a..2da9adab5b 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
@@ -40,6 +40,20 @@ struct icid_id_table icid_tbl[] = {
 	SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
 	SET_ETR_ICID(FSL_ETR_STREAM_ID),
 	SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),
+#ifdef CONFIG_FSL_CAAM
+	SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2),
+	SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3),
+	SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4),
+	SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5),
+	SET_SEC_JR_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 6),
+	SET_SEC_RTIC_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 7),
+	SET_SEC_RTIC_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 8),
+	SET_SEC_RTIC_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 9),
+	SET_SEC_RTIC_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 10),
+	SET_SEC_DECO_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 11),
+	SET_SEC_DECO_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 12),
+	SET_SEC_DECO_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 13),
+#endif
 };
 
 int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index 5be50a17ab..a70c866651 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -8,6 +8,7 @@
 
 #include <asm/types.h>
 #include <fsl_qbman.h>
+#include <fsl_sec.h>
 
 struct icid_id_table {
 	const char *compat;
@@ -82,6 +83,30 @@ void fdt_fixup_icid(void *blob);
 #define SET_FMAN_ICID_ENTRY(_port_id, streamid) \
 	{ .port_id = (_port_id), .icid = (streamid) }
 
+#define SET_SEC_QI_ICID(streamid) \
+	SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
+		(((streamid) << 16) | (streamid)), \
+		offsetof(ccsr_sec_t, qilcr_ls) + \
+		CONFIG_SYS_FSL_SEC_ADDR, \
+		CONFIG_SYS_FSL_SEC_ADDR)
+
+#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \
+	SET_ICID_ENTRY("fsl,sec-v4.0-job-ring", streamid, \
+		(((streamid) << 16) | (streamid)), \
+		offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
+		CONFIG_SYS_FSL_SEC_ADDR, \
+		FSL_SEC_JR##jr_num##_BASE_ADDR)
+
+#define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \
+	SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \
+		offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \
+		CONFIG_SYS_FSL_SEC_ADDR, 0)
+
+#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \
+	SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \
+		offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \
+		CONFIG_SYS_FSL_SEC_ADDR, 0)
+
 extern struct icid_id_table icid_tbl[];
 extern struct fman_icid_id_table fman_icid_tbl[];
 extern int icid_tbl_sz;
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index d22ec70aa5..be0a6ae363 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -200,10 +200,18 @@ struct sys_info {
 
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x700000ull
 #define CONFIG_SYS_FSL_JR0_OFFSET		0x710000ull
+#define FSL_SEC_JR0_OFFSET			CONFIG_SYS_FSL_JR0_OFFSET
+#define FSL_SEC_JR1_OFFSET			0x720000ull
+#define FSL_SEC_JR2_OFFSET			0x730000ull
+#define FSL_SEC_JR3_OFFSET			0x740000ull
 #define CONFIG_SYS_FSL_SEC_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
 #define CONFIG_SYS_FSL_JR0_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
+#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
+#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)
+#define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET)
 
 /* Device Configuration and Pin Control */
 #define DCFG_DCSR_PORCR1		0x0
-- 
2.17.1