[U-Boot] [PATCH v2 21/53] clk: sunxi: Implement AHB bus MMC resets
Jagan Teki
jagan at amarulasolutions.com
Fri Aug 10 06:06:39 UTC 2018
Implement AHB bus MMC resets for all Allwinner SoC
clock drivers via reset map descriptor table.
Cc: Jaehoon Chung <jh80.chung at samsung.com>
Signed-off-by: Jagan Teki <jagan at amarulasolutions.com>
---
drivers/clk/sunxi/clk_a23.c | 3 +++
drivers/clk/sunxi/clk_a31.c | 4 ++++
drivers/clk/sunxi/clk_a64.c | 3 +++
drivers/clk/sunxi/clk_a83t.c | 3 +++
drivers/clk/sunxi/clk_h3.c | 3 +++
drivers/clk/sunxi/clk_r40.c | 4 ++++
drivers/clk/sunxi/clk_v3s.c | 3 +++
7 files changed, 23 insertions(+)
diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
index 0b5406c5b3..183c6275f3 100644
--- a/drivers/clk/sunxi/clk_a23.c
+++ b/drivers/clk/sunxi/clk_a23.c
@@ -38,6 +38,9 @@ static struct ccu_reset_map a23_resets[] = {
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_HSIC] = { 0x0cc, BIT(2) },
+ [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
+ [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
+ [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
[RST_BUS_OTG] = { 0x2c0, BIT(24) },
[RST_BUS_EHCI] = { 0x2c0, BIT(26) },
[RST_BUS_OHCI] = { 0x2c0, BIT(29) },
diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
index 3c807bde77..15076d0e72 100644
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -42,6 +42,10 @@ static struct ccu_reset_map a31_resets[] = {
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_PHY2] = { 0x0cc, BIT(2) },
+ [RST_AHB1_MMC0] = { 0x2c0, BIT(8) },
+ [RST_AHB1_MMC1] = { 0x2c0, BIT(9) },
+ [RST_AHB1_MMC2] = { 0x2c0, BIT(10) },
+ [RST_AHB1_MMC3] = { 0x2c0, BIT(11) },
[RST_AHB1_OTG] = { 0x2c0, BIT(24) },
[RST_AHB1_EHCI0] = { 0x2c0, BIT(26) },
[RST_AHB1_EHCI1] = { 0x2c0, BIT(27) },
diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index 62cd6d6464..9ef9b606d2 100644
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -39,6 +39,9 @@ static struct ccu_reset_map a64_resets[] = {
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_HSIC] = { 0x0cc, BIT(2) },
+ [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
+ [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
+ [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
[RST_BUS_OTG] = { 0x2c0, BIT(23) },
[RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
[RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
index a2e0ac7a26..47b7672e7f 100644
--- a/drivers/clk/sunxi/clk_a83t.c
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -37,6 +37,9 @@ static struct ccu_reset_map a83t_resets[] = {
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_HSIC] = { 0x0cc, BIT(2) },
+ [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
+ [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
+ [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
[RST_BUS_OTG] = { 0x2c0, BIT(24) },
[RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
[RST_BUS_EHCI1] = { 0x2c0, BIT(27) },
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index f467187c01..ad15aaae67 100644
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -46,6 +46,9 @@ static struct ccu_reset_map h3_resets[] = {
[RST_USB_PHY2] = { 0x0cc, BIT(2) },
[RST_USB_PHY3] = { 0x0cc, BIT(3) },
+ [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
+ [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
+ [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
[RST_BUS_OTG] = { 0x2c0, BIT(23) },
[RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
[RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
index 9273f3b7ea..24c26ad3be 100644
--- a/drivers/clk/sunxi/clk_r40.c
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -43,6 +43,10 @@ static struct ccu_reset_map r40_resets[] = {
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_PHY2] = { 0x0cc, BIT(2) },
+ [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
+ [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
+ [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
+ [RST_BUS_MMC3] = { 0x2c0, BIT(11) },
[RST_BUS_OTG] = { 0x2c0, BIT(25) },
[RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
[RST_BUS_EHCI1] = { 0x2c0, BIT(27) },
diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
index e0d757debe..6eeec201a2 100644
--- a/drivers/clk/sunxi/clk_v3s.c
+++ b/drivers/clk/sunxi/clk_v3s.c
@@ -28,6 +28,9 @@ static struct ccu_clk_map v3s_clks[] = {
static struct ccu_reset_map v3s_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
+ [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
+ [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
+ [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
[RST_BUS_OTG] = { 0x2c0, BIT(24) },
};
--
2.18.0.321.gffc6fa0e3
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