[U-Boot] [PATCH v3 6/8] arm: socfpga: gen5: combine some init code for SPL and U-Boot

[Marek Vasut]

On 08/13/2018 09:33 AM, Simon Goldschmidt wrote:
> Some of the code for low level system initialization in SPL's
> board_init_f() and U-Boot's arch_early_init_r() is the same,
> so let's combine it into a single function called from both.
> 
> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>
> ---
> 
> Changes in v3: this patch is new in v3
> Changes in v2: None
> 
>  arch/arm/mach-socfpga/include/mach/misc.h |  4 +++
>  arch/arm/mach-socfpga/misc_gen5.c         | 33 +++++++++++++----------
>  arch/arm/mach-socfpga/spl_gen5.c          | 30 +--------------------
>  3 files changed, 24 insertions(+), 43 deletions(-)
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
> index 7fe77ac8d8..aa7f38d4ea 100644
> --- a/arch/arm/mach-socfpga/include/mach/misc.h
> +++ b/arch/arm/mach-socfpga/include/mach/misc.h
> @@ -27,6 +27,10 @@ unsigned int shared_uart_com_port(const void *blob);
>  unsigned int uart_com_port(const void *blob);
>  #endif
>  
> +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
> +void socfpga_init_bus_mapping(void);
> +#endif
> +
>  void do_bridge_reset(int enable);
>  
>  #endif /* _MISC_H_ */
> diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
> index 848551c73f..32af1a9084 100644
> --- a/arch/arm/mach-socfpga/misc_gen5.c
> +++ b/arch/arm/mach-socfpga/misc_gen5.c
> @@ -175,6 +175,24 @@ static void socfpga_nic301_slave_ns(void)
>  	writel(0x1, &nic301_regs->sdrdata);
>  }
>  
> +void socfpga_init_bus_mapping(void)

Should be called something like socfpga_something_remap_something(),
since it configures the mapping of the first 1 MiB of RAM . otherwise OK

> +{
> +	socfpga_bridges_reset(1);

Drop this from the function, this has nothing to do with the remap settings.

> +	socfpga_nic301_slave_ns();
> +
> +	/*
> +	 * Private components security:
> +	 * U-Boot : configure private timer, global timer and cpu component
> +	 * access as non secure for kernel stage (as required by Linux)
> +	 */
> +	setbits_le32(&scu_regs->sacr, 0xfff);
> +
> +	/* Configure the L2 controller to make SDRAM start at 0 */
> +	writel(0x1, &nic301_regs->remap);	/* remap.mpuzero */
> +	writel(0x1, &pl310->pl310_addr_filter_start);
> +}
> +
>  static u32 iswgrp_handoff[8];
>  
>  int arch_early_init_r(void)
> @@ -193,20 +211,7 @@ int arch_early_init_r(void)
>  	for (i = 0; i < 8; i++)	/* Cache initial SW setting regs */
>  		iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
>  
> -	socfpga_bridges_reset(1);
> -
> -	socfpga_nic301_slave_ns();
> -
> -	/*
> -	 * Private components security:
> -	 * U-Boot : configure private timer, global timer and cpu component
> -	 * access as non secure for kernel stage (as required by Linux)
> -	 */
> -	setbits_le32(&scu_regs->sacr, 0xfff);
> -
> -	/* Configure the L2 controller to make SDRAM start at 0 */
> -	writel(0x1, &nic301_regs->remap);	/* remap.mpuzero */
> -	writel(0x1, &pl310->pl310_addr_filter_start);
> +	socfpga_init_bus_mapping();
>  
>  	/* Add device descriptor to FPGA device table */
>  	socfpga_fpga_add();
> diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
> index 0e685f6ee5..631905fbee 100644
> --- a/arch/arm/mach-socfpga/spl_gen5.c
> +++ b/arch/arm/mach-socfpga/spl_gen5.c
> @@ -5,7 +5,6 @@
>  
>  #include <common.h>
>  #include <asm/io.h>
> -#include <asm/pl310.h>
>  #include <asm/u-boot.h>
>  #include <asm/utils.h>
>  #include <image.h>
> @@ -17,8 +16,6 @@
>  #include <asm/arch/misc.h>
>  #include <asm/arch/scan_manager.h>
>  #include <asm/arch/sdram.h>
> -#include <asm/arch/scu.h>
> -#include <asm/arch/nic301.h>
>  #include <asm/sections.h>
>  #include <debug_uart.h>
>  #include <fdtdec.h>
> @@ -26,12 +23,6 @@
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> -static struct pl310_regs *const pl310 =
> -	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> -static struct scu_registers *scu_regs =
> -	(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
> -static struct nic301_registers *nic301_regs =
> -	(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
>  static const struct socfpga_system_manager *sysmgr_regs =
>  	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>  
> @@ -72,16 +63,6 @@ u32 spl_boot_mode(const u32 boot_device)
>  }
>  #endif
>  
> -static void socfpga_nic301_slave_ns(void)
> -{
> -	writel(0x1, &nic301_regs->lwhps2fpgaregs);
> -	writel(0x1, &nic301_regs->hps2fpgaregs);
> -	writel(0x1, &nic301_regs->acp);
> -	writel(0x1, &nic301_regs->rom);
> -	writel(0x1, &nic301_regs->ocram);
> -	writel(0x1, &nic301_regs->sdrdata);
> -}
> -
>  void board_init_f(ulong dummy)
>  {
>  	const struct cm_config *cm_default_cfg = cm_get_default_config();
> @@ -103,14 +84,7 @@ void board_init_f(ulong dummy)
>  
>  	memset(__bss_start, 0, __bss_end - __bss_start);
>  
> -	socfpga_nic301_slave_ns();
> -
> -	/* Configure ARM MPU SNSAC register. */
> -	setbits_le32(&scu_regs->sacr, 0xfff);
> -
> -	/* Remap SDRAM to 0x0 */
> -	writel(0x1, &nic301_regs->remap);	/* remap.mpuzero */
> -	writel(0x1, &pl310->pl310_addr_filter_start);
> +	socfpga_init_bus_mapping();
>  
>  	debug("Freezing all I/O banks\n");
>  	/* freeze all IO banks */
> @@ -118,8 +92,6 @@ void board_init_f(ulong dummy)
>  
>  	/* Put everything into reset but L4WD0. */
>  	socfpga_per_reset_all();
> -	/* Put FPGA bridges into reset too. */
> -	socfpga_bridges_reset(1);
>  
>  	socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
>  	socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
> 


-- 
Best regards,
Marek Vasut