[U-Boot] [PATCH v4 4/5] arm: socfpga: fix SPL booting from fpga OnChip RAM

[Marek Vasut]

On 08/13/2018 09:34 PM, Simon Goldschmidt wrote:
> To boot from fpga OnChip RAM, some changes are required in SPL
> to ensure the code is linked to the correct address (in contrast
> to QSPI and MMC boot, FPGA boot executes SPL in place instead of
> copying it to SRAM) and that fpga OnChip RAM stays accessible while
> SPL runs (don't disable fpga bridges).
> 
> This adds a new config option (CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA)
> for socfpga gen5 boards.
> 
> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>
> ---
> 
> Changes in v4: Adapted to changed previous patch
> Changes in v3: this patch is new in v3
> Changes in v2: None
> 
>  arch/arm/mach-socfpga/Kconfig     | 12 ++++++++++++
>  arch/arm/mach-socfpga/misc_gen5.c | 11 +++++++++--
>  arch/arm/mach-socfpga/spl_gen5.c  |  6 ++++--
>  include/configs/socfpga_common.h  |  5 +++++
>  4 files changed, 30 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
> index 5c1df2cf1f..a909395aac 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -132,3 +132,15 @@ config SYS_CONFIG_NAME
>  	default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
>  
>  endif
> +
> +if TARGET_SOCFPGA_GEN5
> +
> +config SPL_SOCFPGA_BOOT_FROM_FPGA
> +	bool "Allow booting SPL from FPGA OnChip RAM"
> +	default n
> +	help
> +	  Boot from FPGA: this changes the linker address for SPL code to run
> +	  from FPGA OnChip memory instead of SRAM and ensures FPGA OnChip RAM
> +	  stays accessible while SPL runs.
> +
> +endif
> diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
> index 429c3d6cd5..c82c3584dc 100644
> --- a/arch/arm/mach-socfpga/misc_gen5.c
> +++ b/arch/arm/mach-socfpga/misc_gen5.c
> @@ -187,7 +187,13 @@ void socfpga_sdram_remap_zero(void)
>  	setbits_le32(&scu_regs->sacr, 0xfff);
>  
>  	/* Configure the L2 controller to make SDRAM start at 0 */
> -	writel(0x1, &nic301_regs->remap);	/* remap.mpuzero */
> +	if (CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA)) {
> +		/* remap.mpuzero, keep fpga bridge enabled */
> +		writel(0x9, &nic301_regs->remap);
> +	} else {
> +		/* remap.mpuzero */
> +		writel(0x1, &nic301_regs->remap);
> +	}
>  	writel(0x1, &pl310->pl310_addr_filter_start);
>  }
>  
> @@ -209,7 +215,8 @@ int arch_early_init_r(void)
>  	for (i = 0; i < 8; i++)	/* Cache initial SW setting regs */
>  		iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
>  
> -	socfpga_bridges_reset(1);
> +	if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))
> +		socfpga_bridges_reset(1);
>  
>  	socfpga_sdram_remap_zero();
>  
> diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
> index be318cc0d9..0c7f6a8c84 100644
> --- a/arch/arm/mach-socfpga/spl_gen5.c
> +++ b/arch/arm/mach-socfpga/spl_gen5.c
> @@ -93,7 +93,8 @@ void board_init_f(ulong dummy)
>  	/* Put everything into reset but L4WD0. */
>  	socfpga_per_reset_all();
>  	/* Put FPGA bridges into reset too. */
> -	socfpga_bridges_reset(1);
> +	if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))
> +		socfpga_bridges_reset(1);
>  
>  	socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
>  	socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
> @@ -163,5 +164,6 @@ void board_init_f(ulong dummy)
>  		hang();
>  	}
>  
> -	socfpga_bridges_reset(1);
> +	if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))
> +		socfpga_bridges_reset(1);
>  }
> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
> index d1148b838b..99c5e39086 100644
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -239,7 +239,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>   * 0xFFEz_zzzz ...... Malloc area (grows up to top)
>   * 0xFFE3_FFFF ...... End of SRAM (top)
>   */
> +#if CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA
> +/* SPL executed from FPGA */
> +#define CONFIG_SPL_TEXT_BASE		0xC0000000
> +#else
>  #define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_ADDR
> +#endif
>  #define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_INIT_RAM_SIZE
>  
>  #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)

What about converting the SPL_TEXT_BASE to Kconfig , cfr my comment on
the previous version of the patch ?

-- 
Best regards,
Marek Vasut