[U-Boot] [PATCH] arm: socfpga: Fix SYSMGR_FPGAINTF_EMACx bit mask

[Ley Foon Tan]

On Wed, Aug 15, 2018 at 6:21 PM, Marek Vasut <marex at denx.de> wrote:
> On 08/15/2018 08:20 PM, Ley Foon Tan wrote:
>> Bitmask for EMAC should be bit-0, EMAC1 bit-8 and EMAC2 bit-16.
>>
>> Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>
>> ---
>>  arch/arm/mach-socfpga/include/mach/system_manager_s10.h | 6 +++---
>>  1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
>> index 813dff2..297f9e1 100644
>> --- a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
>> +++ b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
>> @@ -146,9 +146,9 @@ struct socfpga_system_manager {
>>  #define SYSMGR_FPGAINTF_SDMMC        BIT(8)
>>  #define SYSMGR_FPGAINTF_SPIM0        BIT(16)
>>  #define SYSMGR_FPGAINTF_SPIM1        BIT(24)
>> -#define SYSMGR_FPGAINTF_EMAC0        (0x11 << 0)
>> -#define SYSMGR_FPGAINTF_EMAC1        (0x11 << 8)
>> -#define SYSMGR_FPGAINTF_EMAC2        (0x11 << 16)
>
> Wasn't the point here to unreset the OCP bits alongside the standard
> EMAC resets too ?
No, these registers are nothing related to reset. These for FPGA
interface registers if we route the peripheral pins to use FPGA IO.
>
>> +#define SYSMGR_FPGAINTF_EMAC0        BIT(0)
>> +#define SYSMGR_FPGAINTF_EMAC1        BIT(8)
>> +#define SYSMGR_FPGAINTF_EMAC2        BIT(16)
>>
>>  #define SYSMGR_SDMMC_SMPLSEL_SHIFT   4
>>  #define SYSMGR_SDMMC_DRVSEL_SHIFT    0
>>
>
>
> --
Regards
Ley Foon