[U-Boot] [PATCH 3/8] armv8: mmu: Fix "left shift in type int" undefined behavior

[Eugeniu Rosca]

Fix the following UBSAN warnings:

------8<-----
CPU: Renesas Electronics R8A7795 rev 2.0
Model: Renesas Salvator-X board based on r8a7795 ES2.0+
====================================================================
UBSAN: Undefined behaviour in arch/arm/cpu/armv8/cache_v8.c:72:9
left shift of 1 by 31 places cannot be represented in type 'int'
====================================================================
====================================================================
UBSAN: Undefined behaviour in arch/arm/cpu/armv8/cache_v8.c:74:9
left shift of 1 by 31 places cannot be represented in type 'int'
====================================================================
------8<-----

While at it, convert to BIT() macro all current "1 << X" shift
constructs with X >= 15, which may lead to the same UB, if untreated.

Fixes: ad3d6e88a1a4 ("armv8/mmu: Set bits marked RES1 in TCR")
Fixes: 9bb367a590fe ("arm64: Disable TTBR1 maps in EL1")
Signed-off-by: Eugeniu Rosca <erosca at de.adit-jv.com>
---
 arch/arm/include/asm/armv8/mmu.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 62d00d15c26d..b2ce13db0d2b 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -94,11 +94,11 @@
 #define TCR_TG0_4K		(0 << 14)
 #define TCR_TG0_64K		(1 << 14)
 #define TCR_TG0_16K		(2 << 14)
-#define TCR_EPD1_DISABLE	(1 << 23)
+#define TCR_EPD1_DISABLE	BIT(23)
 
-#define TCR_EL1_RSVD		(1 << 31)
-#define TCR_EL2_RSVD		(1 << 31 | 1 << 23)
-#define TCR_EL3_RSVD		(1 << 31 | 1 << 23)
+#define TCR_EL1_RSVD		BIT(31)
+#define TCR_EL2_RSVD		(BIT(31) | BIT(23))
+#define TCR_EL3_RSVD		(BIT(31) | BIT(23))
 
 #ifndef __ASSEMBLY__
 static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
-- 
2.18.0