[U-Boot] r40 enable loading from spi
Ralph Spitzner
rasp at spitzner.org
Sat Dec 1 12:51:58 UTC 2018
small patch to enable loading of u-boot from spi-flash on allwinner r40 boards
( Bananapi_M2_Ultra/Berry)
testet on my Berry, now loading linux from scsi :-)
----
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 3c54f5106d..69f6748f6b 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -973,7 +973,7 @@ config SPL_STACK_R_ADDR
config SPL_SPI_SUNXI
bool "Support for SPI Flash on Allwinner SoCs in SPL"
- depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
+ depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40
help
Enable support for SPI Flash. This option allows SPL to read from
sunxi SPI Flash. It uses the same method as the boot ROM, so does
diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index 043d9f6ead..07e08c184d 100644
--- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
+++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
@@ -54,7 +54,28 @@
/* SUN6I variant of the SPI controller */
/*****************************************************************************/
-#define SUN6I_SPI0_CCTL (0x01C68000 + 0x24)
+/* R40 has the same register map as other sun6i's, but a different base address
+ * and uses PC23 for cs -rasp at spitzner.org 12/'18
+ */
+
+#if IS_ENABLED(ONFIG_MACH_SUN8I_R40)
+#define SUN6I_SPI0_CCTL (0x01c05000 + 0x24)
+#define SUN6I_SPI0_GCR (0x01c05000 + 0x04)
+#define SUN6I_SPI0_TCR (0x01c05000 + 0x08)
+#define SUN6I_SPI0_FIFO_STA (0x01c05000 + 0x1C)
+#define SUN6I_SPI0_MBC (0x01c05000 + 0x30)
+#define SUN6I_SPI0_MTC (0x01c05000 + 0x34)
+#define SUN6I_SPI0_BCC (0x01c05000 + 0x38)
+#define SUN6I_SPI0_TXD (0x01c05000 + 0x200)
+#define SUN6I_SPI0_RXD (0x01c05000 + 0x300)
+
+#define SUN6I_CTL_ENABLE BIT(0)
+#define SUN6I_CTL_MASTER BIT(1)
+#define SUN6I_CTL_SRST BIT(31)
+#define SUN6I_TCR_XCH BIT(31)
+
+#else
+#define SUN6I_SPI0_CCTL (0x01c68000 + 0x24)
#define SUN6I_SPI0_GCR (0x01C68000 + 0x04)
+#define SUN6I_TCR_XCH BIT(31)
+
+#else
+#define SUN6I_SPI0_CCTL (0x01c68000 + 0x24)
#define SUN6I_SPI0_GCR (0x01C68000 + 0x04)
#define SUN6I_SPI0_TCR (0x01C68000 + 0x08)
#define SUN6I_SPI0_FIFO_STA (0x01C68000 + 0x1C)
@@ -68,6 +89,9 @@
#define SUN6I_CTL_MASTER BIT(1)
#define SUN6I_CTL_SRST BIT(31)
#define SUN6I_TCR_XCH BIT(31)
+#endif/*r40 */
+
+
/*****************************************************************************/
@@ -94,7 +118,7 @@ static void spi0_pinmux_setup(unsigned int pin_function)
for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++)
sunxi_gpio_set_cfgpin(pin, pin_function);
- if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I))
+ if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) || IS_ENABLED(CONFIG_MACH_SUN8I_R40))
sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function);
else
sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function);
@@ -103,6 +127,8 @@ static void spi0_pinmux_setup(unsigned int pin_function)
/*
* Setup 6 MHz from OSC24M (because the BROM is doing the same).
*/
+
+
static void spi0_enable_clock(void)
{
/* Deassert SPI0 reset on SUN6I */
diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig
index c18afc839e..0fa9122dc8 100644
--- a/configs/Bananapi_M2_Ultra_defconfig
+++ b/configs/Bananapi_M2_Ultra_defconfig
@@ -20,3 +20,4 @@ CONFIG_AXP_DLDO4_VOLT=2500
CONFIG_AXP_ELDO3_VOLT=1200
CONFIG_SCSI=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+CONFIG_SPL_SPI_SUNXI=y
--
The more you know, the less you do.
-me
-------------- next part --------------
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 3c54f5106d..69f6748f6b 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -973,7 +973,7 @@ config SPL_STACK_R_ADDR
config SPL_SPI_SUNXI
bool "Support for SPI Flash on Allwinner SoCs in SPL"
- depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
+ depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40
help
Enable support for SPI Flash. This option allows SPL to read from
sunxi SPI Flash. It uses the same method as the boot ROM, so does
diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index 043d9f6ead..07e08c184d 100644
--- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
+++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
@@ -54,7 +54,28 @@
/* SUN6I variant of the SPI controller */
/*****************************************************************************/
-#define SUN6I_SPI0_CCTL (0x01C68000 + 0x24)
+/* R40 has the same register map as other sun6i's, but a different base address
+ * and uses PC23 for cs -rasp at spitzner.org 12/'18
+ */
+
+#if IS_ENABLED(ONFIG_MACH_SUN8I_R40)
+#define SUN6I_SPI0_CCTL (0x01c05000 + 0x24)
+#define SUN6I_SPI0_GCR (0x01c05000 + 0x04)
+#define SUN6I_SPI0_TCR (0x01c05000 + 0x08)
+#define SUN6I_SPI0_FIFO_STA (0x01c05000 + 0x1C)
+#define SUN6I_SPI0_MBC (0x01c05000 + 0x30)
+#define SUN6I_SPI0_MTC (0x01c05000 + 0x34)
+#define SUN6I_SPI0_BCC (0x01c05000 + 0x38)
+#define SUN6I_SPI0_TXD (0x01c05000 + 0x200)
+#define SUN6I_SPI0_RXD (0x01c05000 + 0x300)
+
+#define SUN6I_CTL_ENABLE BIT(0)
+#define SUN6I_CTL_MASTER BIT(1)
+#define SUN6I_CTL_SRST BIT(31)
+#define SUN6I_TCR_XCH BIT(31)
+
+#else
+#define SUN6I_SPI0_CCTL (0x01c68000 + 0x24)
#define SUN6I_SPI0_GCR (0x01C68000 + 0x04)
#define SUN6I_SPI0_TCR (0x01C68000 + 0x08)
#define SUN6I_SPI0_FIFO_STA (0x01C68000 + 0x1C)
@@ -68,6 +89,9 @@
#define SUN6I_CTL_MASTER BIT(1)
#define SUN6I_CTL_SRST BIT(31)
#define SUN6I_TCR_XCH BIT(31)
+#endif/*r40 */
+
+
/*****************************************************************************/
@@ -94,7 +118,7 @@ static void spi0_pinmux_setup(unsigned int pin_function)
for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++)
sunxi_gpio_set_cfgpin(pin, pin_function);
- if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I))
+ if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) || IS_ENABLED(CONFIG_MACH_SUN8I_R40))
sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function);
else
sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function);
@@ -103,6 +127,8 @@ static void spi0_pinmux_setup(unsigned int pin_function)
/*
* Setup 6 MHz from OSC24M (because the BROM is doing the same).
*/
+
+
static void spi0_enable_clock(void)
{
/* Deassert SPI0 reset on SUN6I */
diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig
index c18afc839e..0fa9122dc8 100644
--- a/configs/Bananapi_M2_Ultra_defconfig
+++ b/configs/Bananapi_M2_Ultra_defconfig
@@ -20,3 +20,4 @@ CONFIG_AXP_DLDO4_VOLT=2500
CONFIG_AXP_ELDO3_VOLT=1200
CONFIG_SCSI=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+CONFIG_SPL_SPI_SUNXI=y
\ No newline at end of file
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