[U-Boot] [PATCH 00/19] riscv: Adding RISC-V CPU and timer driver

[Bin Meng]

Hi Anup,

On Thu, Dec 6, 2018 at 11:37 AM Anup Patel <anup at brainfault.org> wrote:
>
> Hi Bin,
>
> On Tue, Nov 13, 2018 at 1:47 PM Bin Meng <bmeng.cn at gmail.com> wrote:
> >
> > This adds DM drivers to support RISC-V CPU and timer.
> >
> > The U-Boot RISC-V SBI support is still working in progress.
> > Some patches in this series like adding CSR numbers, exception
> > numbers, are prerequisites for the SBI implementation, but it
> > does no harm to include them as part of this series.
> >
> > This series is dependent on Lukas's riscv series @
> > http://patchwork.ozlabs.org/project/uboot/list/?series=74999
> >
> > This series is available at u-boot-x86/riscv-working for testing.
> >
> >
> > Bin Meng (18):
> >   dm: cpu: Add timebase frequency to the platdata
> >   riscv: qemu: Create a simple-bus driver for the soc node
> >   cpu: Add a RISC-V CPU driver
> >   riscv: Add a SYSCON driver for Core Local Interruptor
> >   timer: Add driver for RISC-V privileged architecture defined timer
> >   riscv: kconfig: Allow platform to specify Kconfig options
> >   riscv: Enlarge the default SYS_MALLOC_F_LEN
> >   riscv: qemu: Probe cpus during boot
> >   riscv: Add CSR numbers
> >   riscv: Add exception codes for xcause register
> >   riscv: Do some basic architecture level cpu initialization
> >   riscv: Move trap handler codes to mtrap.S
> >   riscv: Fix context restore before returning from trap handler
> >   riscv: Return to previous privilege level after trap handling
> >   riscv: Adjust the _exit_trap() position to come before handle_trap()
> >   riscv: Pass correct exception code to _exit_trap()
> >   riscv: Refactor handle_trap() a little for future extension
> >   riscv: Allow U-Boot to run on hart 0 only
> >
> > Lukas Auer (1):
> >   riscv: add Kconfig entries for the code model
> >
>
> I guess you had posted this series before S-mode changes.
>

Yes.

> For your v2, please do try your patches on S-mode too.

Sure.

Regards,
Bin