[U-Boot] [PATCH v2 00/20] riscv: Adding RISC-V CPU and timer driver
Bin Meng
bmeng.cn at gmail.com
Fri Dec 7 14:14:12 UTC 2018
This adds DM drivers to support RISC-V CPU and timer, plus some bug fixes.
This series is available at u-boot-x86/riscv-working for testing.
Changes in v2:
- Use 'Hz' instead of 'HZ'
- add DM_FLAG_PRE_RELOC flag to the simple-bus driver
- pass NULL as the timer device to device_bind_with_driver_data()
- remove the probe to syscon driver in the timer probe, to make the
driver generic, and rely on platform codes to provide the API
riscv_get_time().
- incorporated and reworked Anup's S-mode timer patch
@ http://patchwork.ozlabs.org/patch/1006663/
- rename the driver name to sifive_clint
- save the clint base address to arch specific global data to support
pre-relocation stage
- remove the probe routine
- add riscv_clear_ipi() API
- incorporated and reworked Anup's S-mode timer patch
@ http://patchwork.ozlabs.org/patch/1006663/
- add CMD_CPU as well
- move to arch/riscv/cpu/cpu.c
- new patch to add indirect stringification to csr_xxx ops
- use csr_set() to set MSTATUS_FS
- only enabling the cycle, time, and instret counters
- change to use satp
- rebase on u-boot/master
- drop the patch "riscv: Pass correct exception code to _exit_trap()"
- drop the patch "riscv: Refactor handle_trap() a little for future extension"
- drop the patch "riscv: Allow U-Boot to run on hart 0 only", and
leave the SMP support to Lukas's future patch series
Anup Patel (2):
riscv: Introduce a Kconfig option for machine mode
riscv: Implement riscv_get_time() API using rdtime instruction
Bin Meng (17):
dm: cpu: Add timebase frequency to the platdata
riscv: qemu: Create a simple-bus driver for the soc node
cpu: Add a RISC-V CPU driver
timer: Add generic driver for RISC-V privileged architecture defined
timer
riscv: ax25: Hide the ax25-specific Kconfig option
riscv: Add a SYSCON driver for SiFive's Core Local Interruptor
riscv: qemu: Add platform-specific Kconfig options
riscv: Enlarge the default SYS_MALLOC_F_LEN
riscv: Probe cpus during boot
riscv: Add CSR numbers
riscv: Add exception codes for xcause register
riscv: Add indirect stringification to csr_xxx ops
riscv: Do some basic architecture level cpu initialization
riscv: Move trap handler codes to mtrap.S
riscv: Fix context restore before returning from trap handler
riscv: Return to previous privilege level after trap handling
riscv: Adjust the _exit_trap() position to come before handle_trap()
Lukas Auer (1):
riscv: add Kconfig entries for the code model
arch/riscv/Kconfig | 60 ++++++++-
arch/riscv/Makefile | 9 +-
arch/riscv/cpu/Makefile | 2 +-
arch/riscv/cpu/ax25/Kconfig | 8 +-
arch/riscv/cpu/cpu.c | 33 +++++
arch/riscv/cpu/mtrap.S | 103 +++++++++++++++
arch/riscv/cpu/qemu/Kconfig | 12 ++
arch/riscv/cpu/qemu/cpu.c | 14 +++
arch/riscv/cpu/start.S | 89 -------------
arch/riscv/include/asm/csr.h | 16 +--
arch/riscv/include/asm/encoding.h | 234 +++++++++++++++++++++++++++++++++++
arch/riscv/include/asm/global_data.h | 3 +
arch/riscv/include/asm/syscon.h | 19 +++
arch/riscv/lib/Makefile | 2 +
arch/riscv/lib/interrupts.c | 62 +++++-----
arch/riscv/lib/rdtime.c | 36 ++++++
arch/riscv/lib/sifive_clint.c | 68 ++++++++++
board/emulation/qemu-riscv/Kconfig | 1 +
drivers/cpu/Kconfig | 6 +
drivers/cpu/Makefile | 1 +
drivers/cpu/riscv_cpu.c | 116 +++++++++++++++++
drivers/timer/Kconfig | 8 ++
drivers/timer/Makefile | 1 +
drivers/timer/riscv_timer.c | 57 +++++++++
include/cpu.h | 3 +
25 files changed, 823 insertions(+), 140 deletions(-)
create mode 100644 arch/riscv/cpu/mtrap.S
create mode 100644 arch/riscv/cpu/qemu/Kconfig
create mode 100644 arch/riscv/include/asm/syscon.h
create mode 100644 arch/riscv/lib/rdtime.c
create mode 100644 arch/riscv/lib/sifive_clint.c
create mode 100644 drivers/cpu/riscv_cpu.c
create mode 100644 drivers/timer/riscv_timer.c
--
2.7.4
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