[U-Boot] [RFC PATCH v2 00/11] SF: Migrate to Linux SPI NOR framework

[Simon Goldschmidt]

On Fri, Dec 7, 2018 at 6:58 AM Vignesh R <vigneshr at ti.com> wrote:
>
> On 07/12/18 12:47 AM, Simon Goldschmidt wrote:
> > Am 06.12.2018 um 18:39 schrieb Vignesh R:
> >> On 06/12/18 10:06 PM, Simon Goldschmidt wrote:
> >>> Am 06.12.2018 um 14:54 schrieb Simon Goldschmidt:
> >>>> On Thu, Dec 6, 2018 at 2:45 PM Vignesh R <vigneshr at ti.com> wrote:
> >>>>> On 06/12/18 2:15 AM, Simon Goldschmidt wrote:
> >>>>>> Am 05.12.2018 um 07:55 schrieb Simon Goldschmidt:
> >>>>>>> On Wed, Dec 5, 2018 at 7:51 AM Vignesh R <vigneshr at ti.com> wrote:
> >>>>> [...]
> [...]
> >>> Had a quick test with both standard and tiny in SPL and both configs now
> >>> work on my board. I haven't tested SFDP as you said it does not works on
> >>> Cadence QSPI. (I tested compiling it though, and that works now.)
> >>>
> >
> > After enabling DEBUG in spi-mem.c, I see that we're changing to 4-byte
> > mode (via b7h) instead of using 4-byte opcodes. Unfortunately, this
> > conflicts with the boot rom using the default read opcose in 3-byte mode
> > on warm reboot.
> >
> > Do you plan to change this or would this be fixed by parsing SFDP?
> >
>
> Oh, I see n25q256a entry is missing SPI_NOR_4B_OPCODES flag in the
> spi_nor_ids table. In non SFDP configuration adding SPI_NOR_4B_OPCODES
> flag should avoid sending 0xb7 and use 4-byte opcodes directly. May be
> you could give that a try?

Yes, that did the trick. With SFDP disabled I now see 9Fh (read ID)
followed directly by 0Ch (4-byte FAST READ). Just like it should be.
With SFDP enabled, I get 9Fh, 5Ah, 5Ah and then 0Ch. Both configs do
work fine for me, so:

Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>

Regards,
Simon

>
> >>
> >> I used below hack to test SFDP with Cadence QSPI:
> >
> > Just by accident, I saw that enabling the SFDP config does not seem to
> > break booting. But it still switches to 4-byte mode, so it probably just
> > fails to parse and continues the non-SFDP way?
> >
>
> For stateless 4-byte addressing mode with SFDP, we need to parse JEDEC
> 4-byte Address Instruction Parameter Header and Table (part of JESD216B)
> to get 4 byte addressing opcode.
> We need to port this patch once accepted to Linux kernel:
> https://lore.kernel.org/patchwork/patch/1022200/
>
> >>
> >> diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
> >> index a8af35203035..9dbf9aa7d20c 100644
> >> --- a/drivers/spi/cadence_qspi_apb.c
> >> +++ b/drivers/spi/cadence_qspi_apb.c
> >> @@ -559,7 +559,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
> >>          /* Configure the opcode */
> >>          rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
> >>
> >> -       if (rx_width & SPI_RX_QUAD)
> >> +       if (rx_width & SPI_RX_QUAD && (cmdbuf[0] != 0x5a))
> >
> > But this is Spansion-specific, right?
> >
>
> Nope, SFDP command operates in 1-1-1 mode for all flash devices. But if
> you don't have rx width set to 4 in DT, above hack is not needed and
> SFDP parsing would work fine with Cadence QSPI.
>
>
> --
> Regards
> Vignesh